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mem: DRAMPower trace output
2014-06-30 Andreas Hanssonmem: DRAMPower trace output
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2014-06-30 Andreas Hanssonmem: Add bank and rank indices as fields to the DRAM...
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2014-06-30 Andreas Hanssonmem: Extend DRAM row bits from 16 to 32 for larger...
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2014-06-10 Andreas Hanssonscons: Bump the compiler version to gcc 4.6 and clang 3.0
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2014-05-09 Andreas Hanssonstats: Bump stats for the fixes, and mostly DRAM controller...
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2014-05-09 Andreas Hanssonconfig: Bump DRAM sweep bus speed to match DDR4 config
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2014-05-09 Andreas Hanssontests: Reflect name change in DRAM tests
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2014-05-09 Andreas Hanssonmem: Update DDR3 and DDR4 based on datasheets
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2014-05-09 Andreas Hanssonmem: Add DRAM cycle time
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2014-05-09 Andreas Hanssonmem: Simplify DRAM response scheduling
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2014-05-09 Andreas Hanssonmem: Add precharge all (PREA) to the DRAM controller
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2014-05-09 Andreas Hanssonmem: Remove printing of DRAM params
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2014-05-09 Andreas Hanssonmem: Add tRTP to the DRAM controller
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2014-05-09 Andreas Hanssonmem: Merge DRAM latency calculation and bank state...
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2014-05-09 Andreas Hanssonmem: Add tWR to DRAM activate and precharge constraints
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2014-05-09 Andreas Hanssonmem: Merge DRAM page-management calculations
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2014-05-09 Andreas Hanssonmem: Add DRAM power states to the controller
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2014-05-09 Andreas Hanssonmem: Ensure DRAM refresh respects timings
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2014-05-09 Andreas Hanssonmem: Make DRAM read/write switching less conservative
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2014-04-23 Andreas Hanssonsim: Use correct unit for abort message
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2014-04-22 Andreas Hanssonstats: updates for pc-switcheroo-full due to o3 smt fix
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2014-04-13 Andreas Hanssonscons: Fix python-config parsing by adding strip()
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2014-03-23 Andreas Hanssonstats: Update stats for DRAM changes
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2014-03-23 Andreas Hanssonmem: Track DRAM read/write switching and add hysteresis
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2014-03-23 Andreas Hanssonmem: Rename SimpleDRAM to a more suitable DRAMCtrl
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2014-03-23 Andreas Hanssonmem: Change memory defaults to be more representative
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2014-03-23 Andreas Hanssonmem: DRAM controller tidying up
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2014-03-23 Andreas Hanssonmem: Fix bug in DRAM bytes per activate
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2014-03-23 Andreas Hanssonmem: Limit the accesses to a page before forcing a...
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2014-03-23 Andreas Hanssonmem: Make DRAM write queue draining more aggressive
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2014-03-23 Andreas Hanssonconfig: Add a DRAM efficiency-sweep script
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2014-03-23 Andreas Hanssonmem: More descriptive address-mapping scheme names
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2014-03-23 Andreas Hanssonruby: Move Ruby debug flags to ruby dir and remove...
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2014-03-23 Andreas Hanssonutil: Add support for detection of gzipped packet traces
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2014-03-23 Andreas Hanssonmem: Include the DRAMSim2 wrapper in NULL build
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2014-03-23 Andreas Hanssonext: Fix typo in DRAMSim2 SConscript
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2014-03-23 Andreas Hanssonbase: Fix error message time unit (cycle -> tick)
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2014-03-07 Andreas Hanssoncpu: Make CPU and ThreadContext getters const
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2014-02-24 Andreas Hanssonruby: Simplify RubyPort flow control and routing
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2014-02-19 Andreas Hanssonarm: Bump stats after FS config script update
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2014-02-18 Andreas Hanssonmem: Fix bug in PhysicalMemory use of mmap and munmap
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2014-02-18 Andreas Hanssondev: Include basic devices in NULL ISA build
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2014-02-18 Andreas Hanssonscons: Add PROTOC from the environment
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2014-02-18 Andreas Hanssonmem: Filter cache snoops based on address ranges
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2014-02-18 Andreas Hanssonmem: Add a wrapped DRAMSim2 memory controller
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2014-02-18 Andreas Hanssonutil: Enhance the error messages for packet encode...
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2014-02-18 Andreas Hanssonmem: Fix input to DPRINTF in CommMonitor
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2014-01-24 Andreas Hanssonarch: Make all register index flattening const
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2014-01-24 Andreas Hanssonsim: Expose the current voltage for each object as...
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2014-01-24 Andreas Hanssonsim: Expose the current clock period as a stat
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2014-01-24 Andreas Hanssonconfig: Make the Clock a Tick parameter like Latency...
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2014-01-24 Andreas Hanssonx86: Fix memory leak in table walker
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2014-01-24 Andreas Hanssoncpu: Relax check on squashed non-speculative instructions
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2013-11-15 Andreas Hanssoncpu: Fix Checker register index use
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2013-11-01 Andreas Hanssonstats: Bump stats to match DRAM controller changes
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2013-11-01 Andreas Hanssonmem: Fixes for DRAM stats accounting
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2013-11-01 Andreas Hanssonmem: Fix the LPDDR3 page size
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2013-11-01 Andreas Hanssonmem: Add a simple adaptive version of the open-page...
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2013-11-01 Andreas Hanssonmem: Add tRRD as a timing parameter for the DRAM controller
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2013-11-01 Andreas Hanssonmem: Less conservative tRAS in DRAM configurations
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2013-11-01 Andreas Hanssonmem: Pick the next DRAM request based on bank availability
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2013-11-01 Andreas Hanssonstats: Bump stats after shifting to SimpleMemory
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2013-11-01 Andreas Hanssontest: Use SimpleMemory for atomic full-system tests
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2013-11-01 Andreas Hanssonsim: Clarify the difference between tracing and debugging
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2013-10-17 Andreas Hanssonbuild: Place proto output in the same directory, also...
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2013-10-09 Andreas Hanssonstats: Bump pc-simple-timing-ruby stats
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2013-10-02 Andreas Hanssonkvm: Only include KVM support for supported kernels
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2013-10-02 Andreas Hanssonext: Fix fputils compiler flags to ensure ISO C99
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2013-09-18 Andreas Hanssonmem: Fix scheduling bug in SimpleMemory
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2013-09-18 Andreas Hanssonswig: Warn on use of incompatible swig/gcc combinations
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2013-09-18 Andreas Hanssonswig: Fix issue with circular import in 2.0.9/2.0.10
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2013-09-12 Andreas Hanssonconfig: Add voltage domain to Ruby example scripts
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2013-09-05 Andreas Hanssonsim: Fix clang warning for unused variable
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2013-09-04 Andreas Hanssonutil: Add ini string as tooltip info in dot output
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2013-09-04 Andreas Hanssonutil: Add colours to the dot output
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2013-09-04 Andreas Hanssonutil: Add class name to dot graph and output to svg
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2013-09-04 Andreas Hanssontests: Move ISA-independent tests to the NULL ISA
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2013-09-04 Andreas Hanssonarch: Resurrect the NOISA build target and rename it...
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2013-09-04 Andreas Hanssoncpu: Move the branch predictor out of the BaseCPU
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2013-09-04 Andreas Hanssonarch: Header clean up for NOISA resurrection
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2013-09-04 Andreas Hanssonalpha: Move system virtProxy to Alpha only
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2013-09-04 Andreas Hanssonscons: Enable build on OSX
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2013-08-20 Andreas Hanssoncpu: Fix timing CPU isDrained comment formatting
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2013-08-20 Andreas Hanssonbase: Fix VectorPrint initialisation
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2013-08-19 Andreas Hanssonstats: Cumulative stats update
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2013-08-19 Andreas Hanssonconfig: Command line support for multi-channel memory
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2013-08-19 Andreas Hanssonmem: Change AbstractMemory defaults to match the common...
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2013-08-19 Andreas Hanssonmem: Use STL deque in favour of list for DRAM queues
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2013-08-19 Andreas Hanssonmem: Perform write merging in the DRAM write queue
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2013-08-19 Andreas Hanssoncpu: Fix timing CPU drain check
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2013-08-19 Andreas Hanssonalpha: Check interrupts before quiesce
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2013-08-19 Andreas Hanssonconfig: Move the memory instantiation outside FSConfig
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2013-08-19 Andreas Hanssonmem: Warn instead of panic for tXAW violation
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2013-08-19 Andreas Hanssonmem: Allow disabling of tXAW through a 0 activation...
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2013-08-19 Andreas Hanssonmem: Add an internal packet queue in SimpleMemory
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2013-08-19 Andreas Hanssoncpu: Fix a bug in the O3 CPU introduced by the cache...
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2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level
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2013-07-18 Andreas Hanssonscons: Use python-config instead of distutils
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2013-07-18 Andreas Hanssonsim: Make MaxTick in Python match the one in C++
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2013-06-27 Andreas Hanssonstats: Update stats for monitor, cache and bus changes
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