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cpu: O3 rename using the flatIndex instead of index
2019-01-25 Giacomo Travaglinicpu: O3 rename using the flatIndex instead of index
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Inital vector rename mode depending on A32/A64
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2019-01-25 Giacomo Travaglinicpu: Fix VecElemClass bugs in cpu models
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu: Add VecElem entries in MinorCPU Scoreboard
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Remove unused float operands
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch: Provide traceback when parsing ISA code
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: Implement LoadAcquire/StoreRelease in AArch32
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: IsStoreConditional flag set depending on...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: Remove SWP and SWPB instructions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-22 Giacomo Travagliniarch-arm: Move AArch32 IMPLEMENTATION DEFINED registers
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-16 Giacomo Travagliniarch-arm: Read VMPIDR instead of MPIDR when EL2 is...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-15 Giacomo Travaglinicpu: Fix usage of setArchVecElem
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-15 Giacomo Travagliniarch-arm: Fix usage of RegId constructor for VecElem
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 Giacomo Travaglinibase: Make it possible to convert strings to enums
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Giacomo Travaglinidev-arm: Implement GIC-400 model from GicV2
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Giacomo Travaglinidev-arm: Move VGic from Realview.py to Gic.py
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-19 Giacomo Travagliniarch-arm: Add Crypto in SE mode
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-08 Giacomo Travaglinibase, systemc: Fix clang compilation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-07 Giacomo Travaglinimem: Compile tracePacket only when TRACING_ON is defined
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-06 Giacomo Travagliniext: Build googlemock with googletest
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-06 Giacomo Travagliniext: Import googlemock, release version 1.8.0
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-28 Giacomo Travaglinitests: Convert IniFile unit test to a GTest
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travagliniarch-arm: Print register name when warning on AT instructions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travaglinisim: Move BitUnion overloading to show/parseParams
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travaglinisim: Move paramIn/Out definition to header file
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-12 Giacomo Travaglinisystemc: Push python headers on top of sources
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Deprecate usage of legacy bootloader patching
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: ArmSystem::resetAddr64 renamed to be used...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Implement AArch32 RVBAR
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Remove SCTLR.VE bit
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Refactor ISA::clear by adding a ISA::clear32...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Remove MISCREG commented numbers
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: IMPDEF for SYS instruction with CRn = {11...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Refactor AArch64 MSR/MRS trapping
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Trap to EL2 only if not in Secure State
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Fix HVC trapping beahviour
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: Add have_crypto System parameter
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travaglinicpu: Fix MinorCPU executing Crypto Instructions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto AES
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto SHA
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-02 Giacomo Travaglinisim-se: Set ArmProcess64 hwcaps depending on ID regs
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-02 Giacomo Travaglinisim-se: Different HWCAP for ArmProcess32/64
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID regs as bitunions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Move MiscReg BitUnions into a separate header...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Init AArch64 ID registers in SE mode
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinicpu: Fix typo in header guard for Noncaching cpu
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Enable FIQ signaling for Group0 interrupts...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Create postFiq events for GICv2
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Implement GICv2 GICD_IGROUPR register
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Fix GICv2 cpu interrupt enable flag
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinisim: Extend (UN)SERIALIZE_ARRAY to BitUnions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travaglinidev-arm: Make CpuLocalTimer use standard ArmInterruptPin
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travaglinidev-arm: Take into account PPI enable bit
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travagliniarch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-17 Giacomo Travaglinimem: Implement QoS Proportional Fair policy
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Make GenericTimer use standard ArmInterruptPin
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Factory SimObject for generating ArmInterruptPin
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Create a getter for ArmInterruptPin ID number
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Giacomo Travaglinimem: Implement base QoS Policies.
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Giacomo Travaglinisim: Add System method for MasterID lookup
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-08-24 Giacomo Travaglinicpu: Stream/SubstreamID support in TrafficGen
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-26 Giacomo Travaglinibase: Fix ucontext compilation error for macOS
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-25 Giacomo Travaglinicpu: Warn when (un)serializing a traffic generator
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-25 Giacomo Travaglinicpu: Allow creation of traffic gen from generic SimObjects
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-16 Giacomo Travagliniarch-arm: Introduce ARMv8.1 Virtual Timer System Registers
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-16 Giacomo Travagliniarch-arm: Introduce RAS System Registers
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-28 Giacomo Travaglinibase: Add an asymmetrical Coroutine class
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-22 Giacomo Travagliniarch-arm: AArch32 execution triggering AArch64 SW Break
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-22 Giacomo Travagliniarch-arm: BadMode checking if corresponding EL is implemented
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-21 Giacomo Travaglinicpu: Fix bug introduced by RequestPtr type change
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-14 Giacomo Travagliniarch-arm: Adapting IllegalExecution fault for AArch32
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-14 Giacomo Travagliniarch-arm: Add Illegal Execution flag to PCState
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-14 Giacomo Travagliniarch-arm: Read APSR in User Mode
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-13 Giacomo Travagliniarch-arm: Fix missing Request allocation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-11 Giacomo Travaglinimisc: Substitute pointer to Request with aliased RequestPtr
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: Remove unusued MISCREG_A64_UNIMPL
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: MPIDR.MT = 1 in a multithreaded system
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travaglinicpu: Avoid unnecessary dynamic_pointer_cast in atomic...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: Implement ARMv8.1 TTBR1_EL2 register
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: Add E2H bit to HCR_EL2 System register
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-09 Giacomo Travaglinisim: Remove trailing dot when assigning a master's...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-08 Giacomo Travagliniarch-arm: Map ID_x_EL1 registers to AArch32 version
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-04 Giacomo Travagliniscons: Fix --with-ubsan/asan compilation flags
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-27 Giacomo Travaglinisim,cpu,mem,arch: Introduced MasterInfo data structure
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-19 Giacomo Travagliniarch-arm: Add ARMv8.1 TTBR1_EL2 register
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-19 Giacomo Travagliniarch-arm: Fix Unknown Instruction disassemble
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-19 Giacomo Travagliniarch-arm: Change disassemble when MSR to UNKNOWN register
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-18 Giacomo Travagliniarch-arm: Adding MiscReg Priv (EL1) global flag
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-18 Giacomo Travagliniarch-arm: Using explicit invalidation in TLB
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-17 Giacomo Travagliniarch-arm: Fix secure MiscReg access when EL3 is not...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-10 Giacomo Travagliniarch-arm: Fix mrc,mcr to cop14 disassemble
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-06 Giacomo Travagliniarch-arm: Add support for Tarmac trace generation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-06 Giacomo Travagliniarch-arm: Add support for Tarmac trace-based simulation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-06 Giacomo Travagliniarch-arm: Fix AArch32 branch instructions disassemble
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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