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arch-arm: python3 "/" will always produce a float
2020-03-10 Giacomo Travagliniarch-arm: python3 "/" will always produce a float
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travaglinimisc: Replace basestring with six.string_types
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travaglinimisc: Replace __metaclass__ with six.add_metaclass
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travaglinimisc: string.join has been removed in python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travaglinipython: The new module has been removed in python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-04 Giacomo Travagliniarch-arm: Remove unused getArmSystem helper
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-03 Giacomo Travaglinitests: simple_ruby_test's valid_host is X86 only
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-28 Giacomo Travaglinilearning-gem5: Use zero initialization in hello_goodbye...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-20 Giacomo Travaglinidev-arm: Fix setupBootloader for VExpress_GEM5_V2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-19 Giacomo Travaglinicpu: Fix vector renaming bug
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-19 Giacomo Travagliniarch, arch-arm: Use BaseISA in RenameMode interface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-17 Giacomo Travagliniarch-arm: Be more verbose on load/store construction
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-17 Giacomo Travaglinibase: Use a int to store fgetc return value
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-17 Giacomo Travagliniarch-arm: Fix ArmKVM build
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-17 Giacomo Travaglinicpu: Mark ExecContext::tcBase() as const
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-13 Giacomo Travagliniext: Add failure node to JUnit xml file
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-11 Giacomo Travaglinitests,misc: update TESTING.md documentation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travaglinitests: hello_se using host tag
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travaglinitests: Add --host tag
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travagliniconfigs: Using VExpress_GEM5_V1 as a default for Options.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travagliniarch-arm: LDTRSW was not marked as unpriviledged
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-06 Giacomo Travaglinitests: Move old quick regressions back into their original set
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-04 Giacomo Travagliniarch-arm: Split translateFs to distinguish when MMU...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-22 Giacomo Travaglinitests: Fix python line break in m5_exit test
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-21 Giacomo Travaglinitests: Add a timeout to getremotetime
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-21 Giacomo Travaglinitests: Adding --bin-path option to select tests bin...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-21 Giacomo Travaglinitests: fs/linux/arm passing M5_PATH via commandline
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-09 Giacomo Travaglinibase, gpu-compute: Move gpu AMOs into the generic header
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-08 Giacomo Travagliniarch, base: Move arm AtomicOpFunctor into the generic...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-08 Giacomo Travaglinibase: Move AtomicOpFunctors to a dedicated header
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-07 Giacomo Travaglinisystem-arm: GICv2/GICv3 have different Distributor...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-07 Giacomo Travaglinisystem-arm: Rename ARM bootloader source
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-07 Giacomo Travaglinisystem-arm: Rename ARM bootloader directories
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-06 Giacomo Travaglinidev-arm: Fix SMMUv3 16KB next-level table address masking
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-23 Giacomo Travaglinitests: Always print stderr in gem5 Fixtures
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-20 Giacomo Travagliniconfigs: arm realview(64) regressions using VExpress_GEM5_V1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travagliniarch-arm: Always initialize SVE memData
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travagliniarch-arm: Avoid creating an empty byteEnable vector
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Replace empty byteEnable check with Request::isMasked
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Fix coding style (byteEnable->byte_enable)
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Add byteEnable assertions to readMem and initateMemRead
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Disambuiguate NumFloatV7ArchRegs usage
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Unify VLdmStm behaviour when reg out of index
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Fix NumVecV7ArchRegs value (64->16)
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Reorder arch/arm/registers.hh constants
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinitests: AArch64 Linux as quick regressions (instead...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinimem: Add Request::isMasked to check for byte strobing
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinimem: Add byteEnable copy to Request copy constructor
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-03 Giacomo Travaglinisim-se: Avoid function overloading for syscall implementation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinibase, python: Allow dirname selection for the interpreter
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travagliniconfigs: Add --redirects for syscall emulation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinibase: Fix DPRINTF_UNCONDITIONAL on gem5.fast
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2019-11-27 Giacomo Travagliniconfigs: Add root redirect path in SE mode only when set
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinisim-se: Check Path redirection when mmapping
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travagliniconfigs: Fix baremetal platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-26 Giacomo Travagliniarch-arm: Make the Tarmac parsed registers case insensitive
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-25 Giacomo Travaglinidev-arm: Adjust off_chip ranges in VExpress_GEM5 platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-21 Giacomo Travaglinibase: Remove tests making use of Big/LittleEndianOrder...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-18 Giacomo Travagliniarch-arm: Fix short descriptors cacheability during...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-18 Giacomo Travagliniarch-arm: Fix long descriptors cacheability during...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-14 Giacomo Travaglinitests: Specify a non-default root folder for regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-12 Giacomo Travaglinitests: Using super in arm_generic whenever possible
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-12 Giacomo Travaglinitests: Using super for calling superclass __init__
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-12 Giacomo Travaglinitests: Remove Noncoherent cache from regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-11 Giacomo Travagliniarch-arm: Fix TarmacParser handling of 64bit LD/ST
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-11 Giacomo Travagliniarch-arm: Provide SVE support to the TarmacTracer
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-05 Giacomo Travagliniarch-arm: Annotate original address in CMOs
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-01 Giacomo Travaglinidev-arm: Add SMMUv3 to VExpress_GEM5_V*
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-31 Giacomo Travagliniconfigs: Add baremetal.py example script
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-30 Giacomo Travaglinibase: Name segments after their index
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-22 Giacomo Travagliniconfigs: Clean setupBootLoader signature
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-22 Giacomo Travagliniconfigs: Do not assume bootmem is a System child
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-22 Giacomo Travaglinidev-arm, configs: Using _on_chip_memory for on chip...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-16 Giacomo Travaglinibase: Using scoped string in DPRINTFNR
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-16 Giacomo Travaglinibase: Fix gem5.fast compilation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-15 Giacomo Travaglinidev-arm: Carve out a portion of VExpress_GEM5 for the...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-15 Giacomo Travagliniconfigs: Add simpleSystem helper to generate devices...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-10 Giacomo Travagliniarch-arm: Move generateDtb to ArmSystem
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-10 Giacomo Travaglinidev-arm, configs: Remove RealViewPBX platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-03 Giacomo Travagliniarch-arm: Annotate CM flag in AA64 CM Instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-03 Giacomo Travagliniarch-arm: Set CM bit in DataAbort
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-02 Giacomo Travaglinisim: Mark System::getThreadContext method as const
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-02 Giacomo Travagliniarch-arm: Create helper for sending events (SEV)
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-19 Giacomo Travaglinidev-arm: Conditionally enable HDLcd when doing DTB...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-19 Giacomo Travaglinidev-arm: Add HDLcd DTB autogeneration
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-19 Giacomo Travagliniarch-arm: PSTATE.PAN changes should inval cached regs...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-18 Giacomo Travagliniarch-arm: Fix Data Abort ISS when caused by Atomic...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-18 Giacomo Travagliniarch-arm: ISV bit in DataAbort should check for translation...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-18 Giacomo Travagliniarch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-16 Giacomo Travaglinidev-arm: Allow IOMMU binding to HDLcd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-13 Giacomo Travaglinidev-arm: Store the IOMMU reference from within the...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-13 Giacomo Travaglinidev: Enable DTB IOMMU binding with a DMA object
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Reset HPPI when clearing an LPI
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Add resetHppi method in the GICv3 cpu interface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Cleanup GICv3 initialization
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Initialize GICD_TYPER once at construction...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Writes to IGRPEN1_EL3 triggering update
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Fix GICv3 ITS cmdq wrapping
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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