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dev-arm: Add trusted SP805 to VExpress_GEM5 platform
2020-03-02 Adrian Herreradev-arm: Add trusted SP805 to VExpress_GEM5 platform
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-02 Adrian Herreradev-arm: Add trusted SRAM memory to VExpress_GEM5 platform
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-02 Adrian Herreradev-arm: Add flash0 memory to VExpress_GEM5 platform
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-28 Adrian Herreradev-arm: PL031, fix AMBA ID and clock names
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-28 Giacomo Travaglinilearning-gem5: Use zero initialization in hello_goodbye...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-25 Adrian Herreradev-arm: RealView, add support for off-chip memory
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-25 Adrian Herreradev-arm: default _on_chip_memory on RealView
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-20 Giacomo Travaglinidev-arm: Fix setupBootloader for VExpress_GEM5_V2
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-19 Adrian Herreraarch-arm: ArmISA::clear, inval TLB cached miscregs
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-19 Adrian Herreramisc: pass ThreadContext on ISA clear
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-19 Giacomo Travaglinicpu: Fix vector renaming bug
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-19 Giacomo Travagliniarch, arch-arm: Use BaseISA in RenameMode interface
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-19 Adrian Herreraarch-arm: Fix CNTFRQ_EL0 permission bits
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2020-02-17 Giacomo Travagliniarch-arm: Be more verbose on load/store construction
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-17 Giacomo Travaglinibase: Use a int to store fgetc return value
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-17 Giacomo Travagliniarch-arm: Fix ArmKVM build
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-17 Giacomo Travaglinicpu: Mark ExecContext::tcBase() as const
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-13 Giacomo Travagliniext: Add failure node to JUnit xml file
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-11 Giacomo Travaglinitests,misc: update TESTING.md documentation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travaglinitests: hello_se using host tag
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travaglinitests: Add --host tag
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travagliniconfigs: Using VExpress_GEM5_V1 as a default for Options.py
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travagliniarch-arm: LDTRSW was not marked as unpriviledged
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-06 Giacomo Travaglinitests: Move old quick regressions back into their original set
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-04 Adrian Herreraarch-arm: AArch64 reg access HCR_EL2.E2H filter
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-04 Adrian Herreraarch-arm: reg access permissions highest EL helper
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-04 Giacomo Travagliniarch-arm: Split translateFs to distinguish when MMU...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-31 Ciro Santilliconfigs: allow fs.py and fs_bigLITTLE.py to work without...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-31 Ciro Santilliconfigs: fs.py can take multiple disk images on most...
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-31 Ciro Santilliconfig: add --bootloader to fs.py and fs_bigLITTLE.py
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2020-01-31 Ciro Santillidev-arm: add boot_loader param to RealView setupBootLoader
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-27 Adrian Herrerasystem-arm: AArch64 boot, init CNTFRQ_EL0
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-23 Adrian Herreradev-arm: SP805 peripherals in VExpress_GEM5_Base
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-22 Adrian Herreradev-arm: add Watchdog Module SP805 model
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-22 Adrian Herreradev-arm: VExpress_GEM5_Base, add refclock 32KHz
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-22 Giacomo Travaglinitests: Fix python line break in m5_exit test
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-21 Giacomo Travaglinitests: Add a timeout to getremotetime
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-21 Adrian Herreradev-arm: add FixedClock SimObject
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-21 Giacomo Travaglinitests: Adding --bin-path option to select tests bin...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-21 Giacomo Travaglinitests: fs/linux/arm passing M5_PATH via commandline
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-17 Timothy Hayesconfigs: MESI_Three_level python parameters
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2020-01-17 Timothy Hayesmisc: add Arm build_opts for MESI_Three_Level and MOESI_hammer
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2020-01-15 Adrian Herreraarch-arm: ELIsInHost, check VHE and SecEL2
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-15 Adrian Herreraarch-arm: Virtualization Host Extensions checking
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-14 Adrian Herrerasystem-arm: bigLITTLE with VExpress_GEM5_V2 in dtb
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-10 Adrian Herreradev-arm: VExpress_GEM5_Base, fix daughterboard reference
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-09 Giacomo Travaglinibase, gpu-compute: Move gpu AMOs into the generic header
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-08 Giacomo Travagliniarch, base: Move arm AtomicOpFunctor into the generic...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-08 Giacomo Travaglinibase: Move AtomicOpFunctors to a dedicated header
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-07 Gabor Dozsacpu: Disable O3CPU value forwarding with write strobes
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2020-01-07 Gabor Dozsacpu: Use enums for O3CPU store value forwarding
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2020-01-07 Giacomo Travaglinisystem-arm: GICv2/GICv3 have different Distributor...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-07 Giacomo Travaglinisystem-arm: Rename ARM bootloader source
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-07 Giacomo Travaglinisystem-arm: Rename ARM bootloader directories
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-07 Adrian Herreramisc: Reflect changes of arm bootloader name
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2020-01-06 Adrian Herreraarch-arm: Semihosting, specify files root dir
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-06 Michiel van Toldev-arm: Fix SMMUv3 walkMasks in page table ops
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-06 Giacomo Travaglinidev-arm: Fix SMMUv3 16KB next-level table address masking
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-06 Adrian Herreradev-arm: GICv3, handle GICR_ICFGR0 WI behaviour
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-06 Adrian Herreraconfigs-arm: enable PMU instantiation in CpuCluster
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-03 Giacomo Gabriellicpu: Fix issue with MinorCPU predicated-false mem....
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2020-01-03 Gabor Dozsacpu: Disable MinorCPU value forwarding with write strobes
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2019-12-23 Giacomo Travaglinitests: Always print stderr in gem5 Fixtures
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-20 Giacomo Travagliniconfigs: arm realview(64) regressions using VExpress_GEM5_V1
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-18 Adrian Herreraarch-arm: Semihosting, fix SYS_FLEN
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-18 Adrian Herrerasim: kernelExtras optional load addresses
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-18 Adrian Herrerapython: fix "fatal" usage in fdthelper
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-18 Adrian Herreraarch-arm: Secure EL2 checking
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-18 Adrian Herreraarch-arm: AArch64 trap check, arbitrary ECs/Imms
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-16 Adrian Herrerasim: kernelExtras if no kernel provided
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travagliniarch-arm: Always initialize SVE memData
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travagliniarch-arm: Avoid creating an empty byteEnable vector
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Replace empty byteEnable check with Request::isMasked
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Fix coding style (byteEnable->byte_enable)
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Add byteEnable assertions to readMem and initateMemRead
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Adrian Herreradev-arm: GenericTimer, configurable base and low freqs
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Adrian Herreradev-arm: GenericTimer, freq as 32-bit value
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Disambuiguate NumFloatV7ArchRegs usage
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Unify VLdmStm behaviour when reg out of index
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Fix NumVecV7ArchRegs value (64->16)
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Reorder arch/arm/registers.hh constants
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinitests: AArch64 Linux as quick regressions (instead...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinimem: Add Request::isMasked to check for byte strobing
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinimem: Add byteEnable copy to Request copy constructor
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-03 Giacomo Travaglinisim-se: Avoid function overloading for syscall implementation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-28 Adrian Herreradev-arm: device name in AmbaFake accesses
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinibase, python: Allow dirname selection for the interpreter
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travagliniconfigs: Add --redirects for syscall emulation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinibase: Fix DPRINTF_UNCONDITIONAL on gem5.fast
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2019-11-27 Giacomo Travagliniconfigs: Add root redirect path in SE mode only when set
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinisim-se: Check Path redirection when mmapping
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travagliniconfigs: Fix baremetal platform
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-26 Giacomo Travagliniarch-arm: Make the Tarmac parsed registers case insensitive
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-25 Adrian Herreraarch-arm: default MIDR for Armv8 ISA processors
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-25 Giacomo Travaglinidev-arm: Adjust off_chip ranges in VExpress_GEM5 platform
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-21 Giacomo Travaglinibase: Remove tests making use of Big/LittleEndianOrder...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-18 Adrian Herreraarch-arm: R/W interface to AArch32 HCR2 misc reg
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-18 Giacomo Travagliniarch-arm: Fix short descriptors cacheability during...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-18 Giacomo Travagliniarch-arm: Fix long descriptors cacheability during...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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