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check if register redirection is active, and if vectorisation enabled
2018-09-26
Luke Kenneth Casson...
check if register redirection is active, and if vectorisatio...
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2018-09-26
Luke Kenneth Casson...
comment why sv_insn_t is set up the way it is; add...
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2018-09-26
Luke Kenneth Casson...
easier to #define USING_NOREGS if the opcode does not...
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2018-09-26
Luke Kenneth Casson...
include auto-generated identification of use of registers...
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2018-09-26
Luke Kenneth Casson...
shuffle things around a bit for sv, put rv32/64_name...
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2018-09-25
Luke Kenneth Casson...
skip id_reg.py parsing its own output; stop outputting...
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2018-09-25
Luke Kenneth Casson...
change to instruction template parsing, create one...
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2018-09-25
Luke Kenneth Casson...
add decode.h header to sv.h
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2018-09-25
Luke Kenneth Casson...
rename sv vlen to sv voffs, add csr and reg tables
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2018-09-25
Luke Kenneth Casson...
add reference to vector length in sv
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2018-09-25
Luke Kenneth Casson...
use sv_insn_t class in instruction template
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2018-09-25
Luke Kenneth Casson...
add sv_insn_t class (inherits from insn_t)
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2018-09-25
Luke Kenneth Casson...
argh cant virtualise rd/rs1-3, due to union usage with...
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2018-09-25
Luke Kenneth Casson...
sv: rd, rs1/2/3 become virtual so that sv_insn_t can...
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2018-09-25
Luke Kenneth Casson...
clarify sv cam table
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2018-09-24
Luke Kenneth Casson...
define CSR and register tables for SV
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2018-09-24
Luke Kenneth Casson...
remove unneeded use of AM_CONDITIONAL
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2018-09-24
Luke Kenneth Casson...
add #define for SPIKE_SIMPLEV, re-run autoreconf
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2018-09-24
Luke Kenneth Casson...
create #defines from identified registers, per opcode
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2018-09-24
Luke Kenneth Casson...
clarify docstring on id_regs.py
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2018-09-24
Luke Kenneth Casson...
add function identifying the registers in each emulated...
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2018-09-24
Luke Kenneth Casson...
identify instructions, plan: extract registers
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