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python: Fix param -> int conversion issues
2019-02-18 Giacomo Travagliniarch-arm: Move GICv3 detection at startup time
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-18 Giacomo Travaglinibase: Fix enums checkpointing
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-15 Giacomo Travaglinicpu: Fix fast build broken due to unused variable
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-13 Giacomo Travagliniconfigs: simpoint-profile usable with NonCachingCPUs...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-08 Giacomo Travagliniarch-arm: Fix Virtual interrupts in AArch64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-08 Giacomo Travagliniarch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d0483...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-08 Giacomo Travagliniarch-arm: Allow ArmPPI usage for PMU
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-07 Giacomo Travagliniconfigs, arch-arm: Using AddrRange for Realview mem_regions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-07 Giacomo Travagliniconfigs: Unifiy interpretation of Realview mem_regions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-30 Giacomo Travagliniconfigs: Enable DTB autogeneration in starter_fs.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-30 Giacomo Travagliniarch-arm, configs: Create single instance of DTB autogeneration
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Remove floatReg operand type
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Use VecElem instead of FloatReg for FP instruction
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2019-01-25 Giacomo Travagliniarch: Fix VecElem Operand generation in ISA parser
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu: O3 rename using the flatIndex instead of index
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Inital vector rename mode depending on A32/A64
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2019-01-25 Giacomo Travaglinicpu: Fix VecElemClass bugs in cpu models
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu: Add VecElem entries in MinorCPU Scoreboard
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Remove unused float operands
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch: Provide traceback when parsing ISA code
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: Implement LoadAcquire/StoreRelease in AArch32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: IsStoreConditional flag set depending on...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: Remove SWP and SWPB instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-22 Giacomo Travagliniarch-arm: Move AArch32 IMPLEMENTATION DEFINED registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-16 Giacomo Travagliniarch-arm: Read VMPIDR instead of MPIDR when EL2 is...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-15 Giacomo Travaglinicpu: Fix usage of setArchVecElem
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-15 Giacomo Travagliniarch-arm: Fix usage of RegId constructor for VecElem
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 Giacomo Travaglinibase: Make it possible to convert strings to enums
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Giacomo Travaglinidev-arm: Implement GIC-400 model from GicV2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Giacomo Travaglinidev-arm: Move VGic from Realview.py to Gic.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-19 Giacomo Travagliniarch-arm: Add Crypto in SE mode
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-08 Giacomo Travaglinibase, systemc: Fix clang compilation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-07 Giacomo Travaglinimem: Compile tracePacket only when TRACING_ON is defined
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-06 Giacomo Travagliniext: Build googlemock with googletest
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-06 Giacomo Travagliniext: Import googlemock, release version 1.8.0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-28 Giacomo Travaglinitests: Convert IniFile unit test to a GTest
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travagliniarch-arm: Print register name when warning on AT instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travaglinisim: Move BitUnion overloading to show/parseParams
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travaglinisim: Move paramIn/Out definition to header file
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-12 Giacomo Travaglinisystemc: Push python headers on top of sources
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Deprecate usage of legacy bootloader patching
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: ArmSystem::resetAddr64 renamed to be used...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Implement AArch32 RVBAR
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Remove SCTLR.VE bit
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Refactor ISA::clear by adding a ISA::clear32...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Remove MISCREG commented numbers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: IMPDEF for SYS instruction with CRn = {11...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Refactor AArch64 MSR/MRS trapping
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Trap to EL2 only if not in Secure State
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Fix HVC trapping beahviour
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: Add have_crypto System parameter
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travaglinicpu: Fix MinorCPU executing Crypto Instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto AES
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto SHA
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-02 Giacomo Travaglinisim-se: Set ArmProcess64 hwcaps depending on ID regs
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-02 Giacomo Travaglinisim-se: Different HWCAP for ArmProcess32/64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID regs as bitunions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Move MiscReg BitUnions into a separate header...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Init AArch64 ID registers in SE mode
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinicpu: Fix typo in header guard for Noncaching cpu
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Enable FIQ signaling for Group0 interrupts...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Create postFiq events for GICv2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Implement GICv2 GICD_IGROUPR register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Fix GICv2 cpu interrupt enable flag
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinisim: Extend (UN)SERIALIZE_ARRAY to BitUnions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travaglinidev-arm: Make CpuLocalTimer use standard ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travaglinidev-arm: Take into account PPI enable bit
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travagliniarch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-17 Giacomo Travaglinimem: Implement QoS Proportional Fair policy
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Make GenericTimer use standard ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Factory SimObject for generating ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Create a getter for ArmInterruptPin ID number
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Giacomo Travaglinimem: Implement base QoS Policies.
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Giacomo Travaglinisim: Add System method for MasterID lookup
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-08-24 Giacomo Travaglinicpu: Stream/SubstreamID support in TrafficGen
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-26 Giacomo Travaglinibase: Fix ucontext compilation error for macOS
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-25 Giacomo Travaglinicpu: Warn when (un)serializing a traffic generator
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-25 Giacomo Travaglinicpu: Allow creation of traffic gen from generic SimObjects
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-16 Giacomo Travagliniarch-arm: Introduce ARMv8.1 Virtual Timer System Registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-16 Giacomo Travagliniarch-arm: Introduce RAS System Registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-28 Giacomo Travaglinibase: Add an asymmetrical Coroutine class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-22 Giacomo Travagliniarch-arm: AArch32 execution triggering AArch64 SW Break
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-22 Giacomo Travagliniarch-arm: BadMode checking if corresponding EL is implemented
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-21 Giacomo Travaglinicpu: Fix bug introduced by RequestPtr type change
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-14 Giacomo Travagliniarch-arm: Adapting IllegalExecution fault for AArch32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-14 Giacomo Travagliniarch-arm: Add Illegal Execution flag to PCState
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-14 Giacomo Travagliniarch-arm: Read APSR in User Mode
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-13 Giacomo Travagliniarch-arm: Fix missing Request allocation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-11 Giacomo Travaglinimisc: Substitute pointer to Request with aliased RequestPtr
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: Remove unusued MISCREG_A64_UNIMPL
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: MPIDR.MT = 1 in a multithreaded system
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travaglinicpu: Avoid unnecessary dynamic_pointer_cast in atomic...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: Implement ARMv8.1 TTBR1_EL2 register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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