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mem: Add tRTP to the DRAM controller
2014-05-09
Andreas Hansson
mem: Add tRTP to the DRAM controller
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2014-05-09
Andreas Hansson
mem: Merge DRAM latency calculation and bank state...
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2014-05-09
Andreas Hansson
mem: Add tWR to DRAM activate and precharge constraints
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2014-05-09
Andreas Hansson
mem: Merge DRAM page-management calculations
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2014-05-09
Andreas Hansson
mem: Add DRAM power states to the controller
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2014-05-09
Andreas Hansson
mem: Ensure DRAM refresh respects timings
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2014-05-09
Andreas Hansson
mem: Make DRAM read/write switching less conservative
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2014-04-23
Andreas Hansson
sim: Use correct unit for abort message
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2014-04-22
Andreas Hansson
stats: updates for pc-switcheroo-full due to o3 smt fix
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2014-04-13
Andreas Hansson
scons: Fix python-config parsing by adding strip()
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2014-03-23
Andreas Hansson
stats: Update stats for DRAM changes
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2014-03-23
Andreas Hansson
mem: Track DRAM read/write switching and add hysteresis
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2014-03-23
Andreas Hansson
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
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2014-03-23
Andreas Hansson
mem: Change memory defaults to be more representative
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2014-03-23
Andreas Hansson
mem: DRAM controller tidying up
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2014-03-23
Andreas Hansson
mem: Fix bug in DRAM bytes per activate
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2014-03-23
Andreas Hansson
mem: Limit the accesses to a page before forcing a...
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2014-03-23
Andreas Hansson
mem: Make DRAM write queue draining more aggressive
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2014-03-23
Andreas Hansson
config: Add a DRAM efficiency-sweep script
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2014-03-23
Andreas Hansson
mem: More descriptive address-mapping scheme names
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2014-03-23
Andreas Hansson
ruby: Move Ruby debug flags to ruby dir and remove...
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2014-03-23
Andreas Hansson
util: Add support for detection of gzipped packet traces
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2014-03-23
Andreas Hansson
mem: Include the DRAMSim2 wrapper in NULL build
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2014-03-23
Andreas Hansson
ext: Fix typo in DRAMSim2 SConscript
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2014-03-23
Andreas Hansson
base: Fix error message time unit (cycle -> tick)
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2014-03-07
Andreas Hansson
cpu: Make CPU and ThreadContext getters const
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2014-02-24
Andreas Hansson
ruby: Simplify RubyPort flow control and routing
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2014-02-19
Andreas Hansson
arm: Bump stats after FS config script update
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2014-02-18
Andreas Hansson
mem: Fix bug in PhysicalMemory use of mmap and munmap
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2014-02-18
Andreas Hansson
dev: Include basic devices in NULL ISA build
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2014-02-18
Andreas Hansson
scons: Add PROTOC from the environment
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2014-02-18
Andreas Hansson
mem: Filter cache snoops based on address ranges
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2014-02-18
Andreas Hansson
mem: Add a wrapped DRAMSim2 memory controller
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2014-02-18
Andreas Hansson
util: Enhance the error messages for packet encode...
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2014-02-18
Andreas Hansson
mem: Fix input to DPRINTF in CommMonitor
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2014-01-24
Andreas Hansson
arch: Make all register index flattening const
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2014-01-24
Andreas Hansson
sim: Expose the current voltage for each object as...
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2014-01-24
Andreas Hansson
sim: Expose the current clock period as a stat
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2014-01-24
Andreas Hansson
config: Make the Clock a Tick parameter like Latency...
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2014-01-24
Andreas Hansson
x86: Fix memory leak in table walker
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2014-01-24
Andreas Hansson
cpu: Relax check on squashed non-speculative instructions
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2013-11-15
Andreas Hansson
cpu: Fix Checker register index use
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2013-11-01
Andreas Hansson
stats: Bump stats to match DRAM controller changes
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2013-11-01
Andreas Hansson
mem: Fixes for DRAM stats accounting
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2013-11-01
Andreas Hansson
mem: Fix the LPDDR3 page size
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2013-11-01
Andreas Hansson
mem: Add a simple adaptive version of the open-page...
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2013-11-01
Andreas Hansson
mem: Add tRRD as a timing parameter for the DRAM controller
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2013-11-01
Andreas Hansson
mem: Less conservative tRAS in DRAM configurations
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2013-11-01
Andreas Hansson
mem: Pick the next DRAM request based on bank availability
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2013-11-01
Andreas Hansson
stats: Bump stats after shifting to SimpleMemory
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2013-11-01
Andreas Hansson
test: Use SimpleMemory for atomic full-system tests
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2013-11-01
Andreas Hansson
sim: Clarify the difference between tracing and debugging
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2013-10-17
Andreas Hansson
build: Place proto output in the same directory, also...
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2013-10-09
Andreas Hansson
stats: Bump pc-simple-timing-ruby stats
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2013-10-02
Andreas Hansson
kvm: Only include KVM support for supported kernels
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2013-10-02
Andreas Hansson
ext: Fix fputils compiler flags to ensure ISO C99
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2013-09-18
Andreas Hansson
mem: Fix scheduling bug in SimpleMemory
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2013-09-18
Andreas Hansson
swig: Warn on use of incompatible swig/gcc combinations
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2013-09-18
Andreas Hansson
swig: Fix issue with circular import in 2.0.9/2.0.10
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2013-09-12
Andreas Hansson
config: Add voltage domain to Ruby example scripts
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2013-09-05
Andreas Hansson
sim: Fix clang warning for unused variable
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2013-09-04
Andreas Hansson
util: Add ini string as tooltip info in dot output
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2013-09-04
Andreas Hansson
util: Add colours to the dot output
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2013-09-04
Andreas Hansson
util: Add class name to dot graph and output to svg
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2013-09-04
Andreas Hansson
tests: Move ISA-independent tests to the NULL ISA
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2013-09-04
Andreas Hansson
arch: Resurrect the NOISA build target and rename it...
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2013-09-04
Andreas Hansson
cpu: Move the branch predictor out of the BaseCPU
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2013-09-04
Andreas Hansson
arch: Header clean up for NOISA resurrection
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2013-09-04
Andreas Hansson
alpha: Move system virtProxy to Alpha only
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2013-09-04
Andreas Hansson
scons: Enable build on OSX
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2013-08-20
Andreas Hansson
cpu: Fix timing CPU isDrained comment formatting
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2013-08-20
Andreas Hansson
base: Fix VectorPrint initialisation
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2013-08-19
Andreas Hansson
stats: Cumulative stats update
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2013-08-19
Andreas Hansson
config: Command line support for multi-channel memory
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2013-08-19
Andreas Hansson
mem: Change AbstractMemory defaults to match the common...
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2013-08-19
Andreas Hansson
mem: Use STL deque in favour of list for DRAM queues
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2013-08-19
Andreas Hansson
mem: Perform write merging in the DRAM write queue
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2013-08-19
Andreas Hansson
cpu: Fix timing CPU drain check
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2013-08-19
Andreas Hansson
alpha: Check interrupts before quiesce
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2013-08-19
Andreas Hansson
config: Move the memory instantiation outside FSConfig
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2013-08-19
Andreas Hansson
mem: Warn instead of panic for tXAW violation
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2013-08-19
Andreas Hansson
mem: Allow disabling of tXAW through a 0 activation...
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2013-08-19
Andreas Hansson
mem: Add an internal packet queue in SimpleMemory
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2013-08-19
Andreas Hansson
cpu: Fix a bug in the O3 CPU introduced by the cache...
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2013-07-18
Andreas Hansson
config: Update script to set cache line size on system
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2013-07-18
Andreas Hansson
mem: Set the cache line size on a system level
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2013-07-18
Andreas Hansson
scons: Use python-config instead of distutils
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2013-07-18
Andreas Hansson
sim: Make MaxTick in Python match the one in C++
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2013-06-27
Andreas Hansson
stats: Update stats for monitor, cache and bus changes
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2013-06-27
Andreas Hansson
mem: Remove the cache builder
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2013-06-27
Andreas Hansson
config: Remove Clock parameter multiplication
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2013-06-27
Andreas Hansson
config: Add a BaseSESystem builder for re-use in regressions
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2013-06-27
Andreas Hansson
tests: Prune 00.gzip from the regressions
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2013-06-27
Andreas Hansson
mem: Tidy up the bridge with const and additional checks
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2013-06-27
Andreas Hansson
mem: Fix CommMonitor style and response check
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2013-06-27
Andreas Hansson
mem: Align cache timing to clock edges
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2013-06-27
Andreas Hansson
cpu: Consider instructions waiting for FU completion...
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2013-06-27
Andreas Hansson
mem: Cycles converted to Ticks in atomic cache accesses
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2013-06-27
Andreas Hansson
scons: Identify runs that fail and runs with stats...
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2013-06-27
Andreas Hansson
base: Fix address range granularity calculation
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