| 2018-10-01 |
Giacomo Travaglini | dev-arm: Implement GICv2 GICD_IGROUPR register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-10-01 |
Giacomo Travaglini | dev-arm: Fix GICv2 cpu interrupt enable flag
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-10-01 |
Giacomo Travaglini | sim: Extend (UN)SERIALIZE_ARRAY to BitUnions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-28 |
Giacomo Travaglini | dev-arm: Make CpuLocalTimer use standard ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-28 |
Giacomo Travaglini | dev-arm: Take into account PPI enable bit
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2018-09-28 |
Giacomo Travaglini | arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-17 |
Giacomo Travaglini | mem: Implement QoS Proportional Fair policy
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-10 |
Giacomo Travaglini | dev-arm: Make GenericTimer use standard ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-10 |
Giacomo Travaglini | dev-arm: Factory SimObject for generating ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-10 |
Giacomo Travaglini | dev-arm: Create a getter for ArmInterruptPin ID number
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-07 |
Giacomo Travaglini | mem: Implement base QoS Policies.
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-07 |
Giacomo Travaglini | sim: Add System method for MasterID lookup
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-08-24 |
Giacomo Travaglini | cpu: Stream/SubstreamID support in TrafficGen
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-07-26 |
Giacomo Travaglini | base: Fix ucontext compilation error for macOS
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-07-25 |
Giacomo Travaglini | cpu: Warn when (un)serializing a traffic generator
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-07-25 |
Giacomo Travaglini | cpu: Allow creation of traffic gen from generic SimObjects
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2018-07-16 |
Giacomo Travaglini | arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-07-16 |
Giacomo Travaglini | arch-arm: Introduce RAS System Registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-28 |
Giacomo Travaglini | base: Add an asymmetrical Coroutine class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-22 |
Giacomo Travaglini | arch-arm: AArch32 execution triggering AArch64 SW Break
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-22 |
Giacomo Travaglini | arch-arm: BadMode checking if corresponding EL is implemented
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-21 |
Giacomo Travaglini | cpu: Fix bug introduced by RequestPtr type change
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-14 |
Giacomo Travaglini | arch-arm: Adapting IllegalExecution fault for AArch32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-14 |
Giacomo Travaglini | arch-arm: Add Illegal Execution flag to PCState
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-14 |
Giacomo Travaglini | arch-arm: Read APSR in User Mode
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-13 |
Giacomo Travaglini | arch-arm: Fix missing Request allocation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-11 |
Giacomo Travaglini | misc: Using smart pointers for memory Requests
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-11 |
Giacomo Travaglini | misc: Substitute pointer to Request with aliased RequestPtr
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: Remove unusued MISCREG_A64_UNIMPL
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: MPIDR.MT = 1 in a multithreaded system
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | cpu: Avoid unnecessary dynamic_pointer_cast in atomic...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: Implement ARMv8.1 TTBR1_EL2 register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: Add E2H bit to HCR_EL2 System register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-09 |
Giacomo Travaglini | sim: Remove trailing dot when assigning a master's...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-08 |
Giacomo Travaglini | arch-arm: Map ID_x_EL1 registers to AArch32 version
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-04 |
Giacomo Travaglini | scons: Fix --with-ubsan/asan compilation flags
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-27 |
Giacomo Travaglini | sim,cpu,mem,arch: Introduced MasterInfo data structure
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-19 |
Giacomo Travaglini | arch-arm: Add ARMv8.1 TTBR1_EL2 register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-19 |
Giacomo Travaglini | arch-arm: Fix Unknown Instruction disassemble
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-19 |
Giacomo Travaglini | arch-arm: Change disassemble when MSR to UNKNOWN register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-18 |
Giacomo Travaglini | arch-arm: Adding MiscReg Priv (EL1) global flag
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-18 |
Giacomo Travaglini | arch-arm: Using explicit invalidation in TLB
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-17 |
Giacomo Travaglini | arch-arm: Fix secure MiscReg access when EL3 is not...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-10 |
Giacomo Travaglini | arch-arm: Fix mrc,mcr to cop14 disassemble
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-06 |
Giacomo Travaglini | arch-arm: Add support for Tarmac trace generation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-06 |
Giacomo Travaglini | arch-arm: Add support for Tarmac trace-based simulation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-06 |
Giacomo Travaglini | arch-arm: Fix AArch32 branch instructions disassemble
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-06 |
Giacomo Travaglini | arch-arm: Fix secure write of SCTLR when EL3 is AArch64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-06 |
Giacomo Travaglini | arch-arm: Correct mcrr,mrrc disassemble
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-23 |
Giacomo Travaglini | arch-arm: Distinguish IS TLBI from non-IS
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-23 |
Giacomo Travaglini | arch-arm: Created function for TLB ASID Invalidation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-14 |
Giacomo Travaglini | tests: Add missing print replacements in tests subdir
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2018-03-14 |
Giacomo Travaglini | arch-arm: ERET from AArch64 to AArch32 ignore MSBs
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-12 |
Giacomo Travaglini | arch-arm: Adding IPA-Based Invalidating instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-12 |
Giacomo Travaglini | arch-arm: Implement missing aarch32 TLBI registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-09 |
Giacomo Travaglini | tests: Python regression scripts using new print function
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-08 |
Giacomo Travaglini | arch-arm: Enable Debug IFSC when faulting to aarch64...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-08 |
Giacomo Travaglini | arch-arm: Fix FSC generation in AbortFault
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-08 |
Giacomo Travaglini | arch-arm: Introduce update method in ArmFault class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2018-03-08 |
Giacomo Travaglini | arch-arm: Fix PCAlignmentFault routing to Hypervisor
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: Make hlt64 a mem barrier with semihosting
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: Add AArch32 HLT Semihosting interface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: Add AArch32 SVC Semihosting interface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: Adding isa templates for semihosting ops
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: HLT using immediate when checking for semihosting
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-19 |
Giacomo Travaglini | arch-arm: Semihosting not available in syscall emulation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-16 |
Giacomo Travaglini | arch-arm: IMPLEMENTATION DEFINED register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-16 |
Giacomo Travaglini | arch-arm: Arch regs and pseudo regs distinction
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-16 |
Giacomo Travaglini | arch-arm: Change ArmFault cast from reinterpret to...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2018-02-09 |
Giacomo Travaglini | sim: Remove _numContexts member in System class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-08 |
Giacomo Travaglini | arch-arm: Correct SecureMonitorTrap vals for aarch32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-08 |
Giacomo Travaglini | arch-arm: Don't change PSTATE in Illegal Exception...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2018-02-07 |
Giacomo Travaglini | arch-arm: Change function name for banked miscregs
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2018-02-07 |
Giacomo Travaglini | arch-arm: Fix AArch32 SETEND Instruction
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2018-02-07 |
Giacomo Travaglini | arch-arm: Correct Illegal Exception Return detection
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2018-02-07 |
Giacomo Travaglini | arch-arm: ELUsingAArch32K from armarm pseudocode
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-07 |
Giacomo Travaglini | arch-arm: isSecureBelow from armarm pseudocode
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2018-02-05 |
Giacomo Travaglini | cpu: MinorCPU handling IsSquashAfter flag
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-05 |
Giacomo Travaglini | arch-arm: Removing Serializing flag from ISB
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2017-12-21 |
Giacomo Travaglini | arch-arm: Fixed WFE/WFI trapping behaviour
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-12-21 |
Giacomo Travaglini | arch-arm: Hyp routed undef fault need to change its...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-12-21 |
Giacomo Travaglini | arch-arm: Fix StaticInst encoding() method
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-12-19 |
Giacomo Travaglini | arch-arm: Instruction size methods in StaticInst class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2017-12-19 |
Giacomo Travaglini | arch-arm: Change casting type from reinterpret to static
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-12-08 |
Giacomo Travaglini | arm: Change access permission in TPIDRURO and TPIDRURW
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-12-01 |
Giacomo Travaglini | arm: Enable ns registers access in secure mode
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2017-11-28 |
Giacomo Travaglini | arch-arm: Add haveEL pseudocode function
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-11-28 |
Giacomo Travaglini | arch-arm: Add assertions when extracting an ArmSystem...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-11-22 |
Giacomo Travaglini | arch-arm: HVC instruction undefined in secure EL1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-11-21 |
Giacomo Travaglini | scons: Build error introduced by site_tools/default.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-11-21 |
Giacomo Travaglini | arch-arm: Fix MCR/MRC disassemble
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-11-21 |
Giacomo Travaglini | arch-arm: Fix MSR/MRS disassemble
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-11-15 |
Giacomo Travaglini | arch-arm: Dsb instruction shouldn't flush the pipeline
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-11-15 |
Giacomo Travaglini | arch-arm: Writes to DCCMVAC shouldn't flush pipeline
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-11-15 |
Giacomo Travaglini | arch-arm: Removing FlushPipe fault, using SquashAfter
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-11-15 |
Giacomo Travaglini | arm: Add support for armv8 CRC32 instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-11-13 |
Giacomo Travaglini | arch-arm: Interface for the ArmStaticInst intWidth...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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