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arch-arm: Remove floatReg operand type
2019-01-25 Giacomo Travagliniarch-arm: Remove floatReg operand type
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Use VecElem instead of FloatReg for FP instruction
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2019-01-25 Giacomo Travagliniarch: Fix VecElem Operand generation in ISA parser
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu: O3 rename using the flatIndex instead of index
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Inital vector rename mode depending on A32/A64
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2019-01-25 Giacomo Travaglinicpu: Fix VecElemClass bugs in cpu models
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu: Add VecElem entries in MinorCPU Scoreboard
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Remove unused float operands
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch: Provide traceback when parsing ISA code
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Nicholas Lindsaypython: Always throw TypeError on slave-slave connections
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2019-01-24 Rekai Gonzalez-Alber... cpu-o3: O3 LSQ Generalisation
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2019-01-23 Giacomo Travagliniarch-arm: Implement LoadAcquire/StoreRelease in AArch32
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: IsStoreConditional flag set depending on...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: Remove SWP and SWPB instructions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-22 Giacomo Travagliniarch-arm: Move AArch32 IMPLEMENTATION DEFINED registers
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-22 Sascha Bischoffmem: Add tryTiming suppport to CommMonitor
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2019-01-16 Giacomo Travagliniarch-arm: Read VMPIDR instead of MPIDR when EL2 is...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-16 Anouk Van Laerarch-arm: Added TLBI_ALL EL2 instruction
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-15 Giacomo Travaglinicpu: Fix usage of setArchVecElem
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-15 Giacomo Travagliniarch-arm: Fix usage of RegId constructor for VecElem
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 Jairo Balartdev-arm: Add a VExpress_GEM5_V2 platform with GICv3...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 Jairo Balartdev-arm: Add a GICv3 model
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 Giacomo Travaglinibase: Make it possible to convert strings to enums
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Jan-Peter Larssondev, arm: Warn on PL011 DMA disable
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Anouk Van Laerdev-arm: Added VGIC GICV_IIDR response
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Giacomo Travaglinidev-arm: Implement GIC-400 model from GicV2
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Giacomo Travaglinidev-arm: Move VGic from Realview.py to Gic.py
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Anouk Van Laerdev-arm: Added unimplemented GICv2 GICC_DIR
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-03 Curtis Dunhamarm: properly handle RES0/1 for SCTLRs
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-19 Giacomo Travagliniarch-arm: Add Crypto in SE mode
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-08 Giacomo Travaglinibase, systemc: Fix clang compilation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-07 Giacomo Travaglinimem: Compile tracePacket only when TRACING_ON is defined
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-06 Matteo Andreozziext: Remove unused bankwiseMode variable
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2018-12-06 Rekai Gonzalez-Alber... base: Ported circlebuf to CircularQueue
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-06 Rekai Gonzalez-Alber... base: Iterable CircularQueue implementation
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2018-12-06 Giacomo Travagliniext: Build googlemock with googletest
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-06 Giacomo Travagliniext: Import googlemock, release version 1.8.0
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-03 Giacomo Gabriellibase: Add type alias for raw pointer in RefCountingPtr
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2018-11-28 Matteo Andreozziarch-arm: clang compilation fixes
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-28 Giacomo Travaglinitests: Convert IniFile unit test to a GTest
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-16 Matteo Andreozzimem: avoid calling regStat twice on a QoSPolicy
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travagliniarch-arm: Print register name when warning on AT instructions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travaglinisim: Move BitUnion overloading to show/parseParams
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travaglinisim: Move paramIn/Out definition to header file
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-12 Giacomo Travaglinisystemc: Push python headers on top of sources
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Deprecate usage of legacy bootloader patching
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: ArmSystem::resetAddr64 renamed to be used...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Implement AArch32 RVBAR
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Remove SCTLR.VE bit
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Refactor ISA::clear by adding a ISA::clear32...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Remove MISCREG commented numbers
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: IMPDEF for SYS instruction with CRn = {11...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Refactor AArch64 MSR/MRS trapping
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Trap to EL2 only if not in Secure State
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Fix HVC trapping beahviour
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-17 Adrien Pesledev-arm: Don't panic when EOIR a non active PPI
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-17 Adrien Pesledev-arm: Fix Gicv2 distributor group register
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: Add have_crypto System parameter
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travaglinicpu: Fix MinorCPU executing Crypto Instructions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto AES
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto SHA
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Matt Horsnellarch-arm: AArch32 Crypto AES
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Matt Horsnellarch-arm: AArch32 Crypto SHA
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-08 Matteo Andreozziarch-arm: Mark ArmProcess method as override
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-02 Giacomo Travaglinisim-se: Set ArmProcess64 hwcaps depending on ID regs
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-02 Giacomo Travaglinisim-se: Different HWCAP for ArmProcess32/64
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID regs as bitunions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Move MiscReg BitUnions into a separate header...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Init AArch64 ID registers in SE mode
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinicpu: Fix typo in header guard for Noncaching cpu
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Enable FIQ signaling for Group0 interrupts...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Create postFiq events for GICv2
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Implement GICv2 GICD_IGROUPR register
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Fix GICv2 cpu interrupt enable flag
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Adrien Pesledev-arm: Add basic support for level sensitive SPIs...
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2018-10-01 Giacomo Travaglinisim: Extend (UN)SERIALIZE_ARRAY to BitUnions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travaglinidev-arm: Make CpuLocalTimer use standard ArmInterruptPin
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travaglinidev-arm: Take into account PPI enable bit
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travagliniarch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-17 Giacomo Travaglinimem: Implement QoS Proportional Fair policy
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Make GenericTimer use standard ArmInterruptPin
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Factory SimObject for generating ArmInterruptPin
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Andreas Sandbergarm: Use the interrupt adaptor in the PMU
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Andreas Sandbergarm: Add support for tracking TCs in ISA devices
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Andreas Sandbergdev, arm: Add misc reg tracing to the generic timer
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Create a getter for ArmInterruptPin ID number
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Matteo Andreozzimem: Make DRAMCtrl a QoS-aware Memory Controller
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Giacomo Travaglinimem: Implement base QoS Policies.
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Matteo Andreozzimem: Add a simple QoS-aware Memory Controller
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Matteo Andreozzimem: Add a QoS-aware Memory Controller type
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Giacomo Travaglinisim: Add System method for MasterID lookup
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-08-24 Giacomo Travaglinicpu: Stream/SubstreamID support in TrafficGen
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-08-24 Michiel W. van Tolcpu: Turn BaseTrafficGen numSuppressed into a stat
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2018-08-22 Stanislaw Czerniawskimem: Add StreamID and SubstreamID
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-08-10 Giacomo Gabrielliarm: Add support for RCpc load-acquire instructions...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-26 Giacomo Travaglinibase: Fix ucontext compilation error for macOS
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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