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2018-07-28	Alec Roelke	arch-riscv: Add xret instructions Maintainer: Alec Roelke <alec.roelke@gmail.com>	commit \| commitdiff \| tree
2018-07-28	Alec Roelke	arch-riscv: Add support for trap value register Maintainer: Alec Roelke <alec.roelke@gmail.com>	commit \| commitdiff \| tree
2018-07-28	Alec Roelke	arch-riscv: Add support for fault handling Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2018-05-12	Alec Roelke	arch-riscv: Update CSR implementations Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2018-02-19	Alec Roelke	arch-riscv: Fix compressed branch op offset Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2018-01-16	Alec Roelke	arch-riscv: Fix floating-poing op classes Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2018-01-16	Alec Roelke	arch-riscv: Fix floating-point conversion bugs Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2018-01-11	Alec Roelke	arch-riscv: Don't crash when printing unknown CSRs Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2018-01-10	Alec Roelke	arch-riscv: Make use of ImmOp's polymorphism Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2018-01-05	Alec Roelke	arch-riscv: Correct syscall argument reg count Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2018-01-04	Alec Roelke	arch-riscv: Remove "magic" syscall number constant Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-12-14	Alec Roelke	arch-riscv: Define AT_RANDOM properly Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-12-14	Alec Roelke	arch-riscv: Increase maximum stack size Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-12-07	Alec Roelke	arch-riscv: Move compressed ops out of ISA Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-11-30	Alec Roelke	arch-riscv: use sext rather than manual masks Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-11-30	Alec Roelke	arch-riscv: Remove spaces around ea_code Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-11-29	Alec Roelke	arch-riscv: Add missing license paragraphs	commit \| commitdiff \| tree
2017-11-29	Alec Roelke	arch-riscv: Remove static parts of AMOs out of ISA Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-11-29	Alec Roelke	arch-riscv: Move parts of mem insts out of ISA Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-11-29	Alec Roelke	arch-riscv: Move unknown out of ISA description Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-11-29	Alec Roelke	arch-riscv: Move standard ops out of ISA Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-11-28	Alec Roelke	arch-riscv: Move static_inst into a directory Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-11-22	Alec Roelke	arch-riscv: Add missing system calls Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-11-22	Alec Roelke	sim-se: Add default to SyscallDesc constructor	commit \| commitdiff \| tree
2017-11-06	Alec Roelke	sim-se: Add prlimit system call	commit \| commitdiff \| tree
2017-07-17	Alec Roelke	riscv: Define register index constants using literals Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-07-14	Alec Roelke	tests: Upate RISC-V binaries and results	commit \| commitdiff \| tree
2017-07-14	Alec Roelke	riscv: Fix bugs with RISC-V decoder and detailed CPUs Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-07-14	Alec Roelke	riscv: Add unused attribute to some registers.hh constants Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-07-11	Alec Roelke	arch-riscv,tests: Add insttests for RV64C	commit \| commitdiff \| tree
2017-07-11	Alec Roelke	arch-riscv: Add support for compressed extension RV64C Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-07-11	Alec Roelke	arch-riscv: Restructure ISA description Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-06-05	Alec Roelke	tests: Update RISC-V hello test and stats	commit \| commitdiff \| tree
2017-05-23	Alec Roelke	arch-riscv: Fix bad stack initialization Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-05-15	Alec Roelke	cpu: fix problem with forwarding and locked load	commit \| commitdiff \| tree
2017-04-11	Alec Roelke	riscv: Fix crashes with large or frequent mmaps Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-04-05	Alec Roelke	riscv: fix Linux problems with LR and SC ops Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-04-05	Alec Roelke	riscv: fix compatibility with Linux toolchain Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-04-05	Alec Roelke	riscv: add remote gdb support Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-04-05	Alec Roelke	riscv: fix error on memory op address overflow Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-04-05	Alec Roelke	riscv: enable unaligned memory accesses Maintainer: Alec Roelke <ar4jc@virginia.edu>	commit \| commitdiff \| tree
2017-02-13	Alec Roelke	riscv: Remove ECALL tests from insttest	commit \| commitdiff \| tree
2017-01-27	Alec Roelke	riscv: Fix crash when syscall argument reg index is...	commit \| commitdiff \| tree
2016-11-30	Alec Roelke	riscv: [Patch 8/5] Added some regression tests to RISC-V Signed-off by: Alec Roelke	commit \| commitdiff \| tree
2016-11-30	Alec Roelke	riscv: [Patch 7/5] Corrected LRSC semantics Signed-off by: Alec Roelke	commit \| commitdiff \| tree
2016-11-30	Alec Roelke	riscv: [Patch 6/5] Improve Linux emulation for RISC-V Signed-off by: Alec Roelke	commit \| commitdiff \| tree
2016-11-30	Alec Roelke	riscv: [Patch 5/5] Added missing support for timing... Signed-off by: Alec Roelke	commit \| commitdiff \| tree
2016-11-30	Alec Roelke	riscv: [Patch 4/5] Added RISC-V atomic memory extension... Signed-off by: Alec Roelke	commit \| commitdiff \| tree
2016-11-30	Alec Roelke	riscv: [Patch 3/5] Added RISCV floating point extensions... Signed-off by: Alec Roelke	commit \| commitdiff \| tree
2016-11-30	Alec Roelke	riscv: [Patch 2/5] Added RISC-V multiply extension... Signed-off by: Alec Roelke	commit \| commitdiff \| tree
2016-11-30	Alec Roelke	arch: [Patch 1/5] Added RISC-V base instruction set... Signed-off by: Alec Roelke	commit \| commitdiff \| tree

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