2018-09-29 |
Luke Kenneth Casson... | revert addition of svsetvl as an actual opcode, add...
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2018-09-29 |
Luke Kenneth Casson... | Revert "sv setvl as a csr not going to work, add getvl...
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2018-09-29 |
Luke Kenneth Casson... | Revert "manually add svsetvl instruction"
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2018-09-28 |
Luke Kenneth Casson... | manually add svsetvl instruction
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commit | commitdiff | tree |
2018-09-28 |
Luke Kenneth Casson... | sv setvl as a csr not going to work, add getvl only
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2018-09-27 |
Luke Kenneth Casson... | adding sv vector length CSR to processor state, and...
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2018-09-27 |
Luke Kenneth Casson... | add sv predication function
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2018-09-26 |
Luke Kenneth Casson... | save some cpu cycles by |ing the checks for vectorop...
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2018-09-26 |
Luke Kenneth Casson... | whoops vectorop has to be |= not &= to accumulate ...
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2018-09-26 |
Luke Kenneth Casson... | cache the sv redirected register values on each loop
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2018-09-26 |
Luke Kenneth Casson... | remembered that the use of sv registers have to be...
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2018-09-26 |
Luke Kenneth Casson... | clarify comments on (key strategic) sv_insn_t::remap...
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2018-09-26 |
Luke Kenneth Casson... | actually implement sv register re-mapping
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2018-09-26 |
Luke Kenneth Casson... | ok this is tricky: an extra parameter has to be passed...
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2018-09-26 |
Luke Kenneth Casson... | move sv remap function to sv.cc (not inline)
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2018-09-26 |
Luke Kenneth Casson... | check if register redirection is active, and if vectorisatio...
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2018-09-26 |
Luke Kenneth Casson... | comment why sv_insn_t is set up the way it is; add...
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2018-09-26 |
Luke Kenneth Casson... | easier to #define USING_NOREGS if the opcode does not...
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2018-09-26 |
Luke Kenneth Casson... | include auto-generated identification of use of registers...
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2018-09-26 |
Luke Kenneth Casson... | shuffle things around a bit for sv, put rv32/64_name...
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2018-09-25 |
Luke Kenneth Casson... | skip id_reg.py parsing its own output; stop outputting...
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2018-09-25 |
Luke Kenneth Casson... | change to instruction template parsing, create one...
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2018-09-25 |
Luke Kenneth Casson... | add decode.h header to sv.h
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2018-09-25 |
Luke Kenneth Casson... | rename sv vlen to sv voffs, add csr and reg tables
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2018-09-25 |
Luke Kenneth Casson... | add reference to vector length in sv
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2018-09-25 |
Luke Kenneth Casson... | use sv_insn_t class in instruction template
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2018-09-25 |
Luke Kenneth Casson... | add sv_insn_t class (inherits from insn_t)
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2018-09-25 |
Luke Kenneth Casson... | argh cant virtualise rd/rs1-3, due to union usage with...
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2018-09-25 |
Luke Kenneth Casson... | sv: rd, rs1/2/3 become virtual so that sv_insn_t can...
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2018-09-25 |
Luke Kenneth Casson... | clarify sv cam table
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2018-09-24 |
Luke Kenneth Casson... | define CSR and register tables for SV
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2018-09-24 |
Luke Kenneth Casson... | remove unneeded use of AM_CONDITIONAL
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2018-09-24 |
Luke Kenneth Casson... | add #define for SPIKE_SIMPLEV, re-run autoreconf
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2018-09-24 |
Luke Kenneth Casson... | create #defines from identified registers, per opcode
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2018-09-24 |
Luke Kenneth Casson... | clarify docstring on id_regs.py
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2018-09-24 |
Luke Kenneth Casson... | add function identifying the registers in each emulated...
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2018-09-24 |
Luke Kenneth Casson... | identify instructions, plan: extract registers
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