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2018-09-27	Luke Kenneth Casson...	add sv predication function	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	save some cpu cycles by \|ing the checks for vectorop...	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	whoops vectorop has to be \|= not &= to accumulate ...	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	cache the sv redirected register values on each loop	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	remembered that the use of sv registers have to be...	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	clarify comments on (key strategic) sv_insn_t::remap...	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	actually implement sv register re-mapping	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	ok this is tricky: an extra parameter has to be passed...	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	move sv remap function to sv.cc (not inline)	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	check if register redirection is active, and if vectorisatio...	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	comment why sv_insn_t is set up the way it is; add...	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	easier to #define USING_NOREGS if the opcode does not...	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	include auto-generated identification of use of registers...	commit \| commitdiff \| tree
2018-09-26	Luke Kenneth Casson...	shuffle things around a bit for sv, put rv32/64_name...	commit \| commitdiff \| tree
2018-09-25	Luke Kenneth Casson...	skip id_reg.py parsing its own output; stop outputting...	commit \| commitdiff \| tree
2018-09-25	Luke Kenneth Casson...	change to instruction template parsing, create one...	commit \| commitdiff \| tree
2018-09-25	Luke Kenneth Casson...	add decode.h header to sv.h	commit \| commitdiff \| tree
2018-09-25	Luke Kenneth Casson...	rename sv vlen to sv voffs, add csr and reg tables	commit \| commitdiff \| tree
2018-09-25	Luke Kenneth Casson...	add reference to vector length in sv	commit \| commitdiff \| tree
2018-09-25	Luke Kenneth Casson...	use sv_insn_t class in instruction template	commit \| commitdiff \| tree
2018-09-25	Luke Kenneth Casson...	add sv_insn_t class (inherits from insn_t)	commit \| commitdiff \| tree
2018-09-25	Luke Kenneth Casson...	argh cant virtualise rd/rs1-3, due to union usage with...	commit \| commitdiff \| tree
2018-09-25	Luke Kenneth Casson...	sv: rd, rs1/2/3 become virtual so that sv_insn_t can...	commit \| commitdiff \| tree
2018-09-25	Luke Kenneth Casson...	clarify sv cam table	commit \| commitdiff \| tree
2018-09-24	Luke Kenneth Casson...	define CSR and register tables for SV	commit \| commitdiff \| tree
2018-09-24	Luke Kenneth Casson...	remove unneeded use of AM_CONDITIONAL	commit \| commitdiff \| tree
2018-09-24	Luke Kenneth Casson...	add #define for SPIKE_SIMPLEV, re-run autoreconf	commit \| commitdiff \| tree
2018-09-24	Luke Kenneth Casson...	create #defines from identified registers, per opcode	commit \| commitdiff \| tree
2018-09-24	Luke Kenneth Casson...	clarify docstring on id_regs.py	commit \| commitdiff \| tree
2018-09-24	Luke Kenneth Casson...	add function identifying the registers in each emulated...	commit \| commitdiff \| tree
2018-09-24	Luke Kenneth Casson...	identify instructions, plan: extract registers	commit \| commitdiff \| tree

Simple-V augmented version of spike

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