projects
/
riscv-isa-sim.git
/ search
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
Merge pull request #108 from riscv/dtc-error
2017-03-30
Wesley W. Terpstra
fdt: move interrupt controller into its own node
commit
|
commitdiff
|
tree
2017-03-22
Wesley W. Terpstra
riscv: replace rtc device with a real clint implementation
commit
|
commitdiff
|
tree
2017-03-22
Wesley W. Terpstra
sim: declare cores as interrupt-controllers for clint
commit
|
commitdiff
|
tree
2017-03-21
Wesley W. Terpstra
bootrom: set a0 to hartid and a1 to dtb before boot
commit
|
commitdiff
|
tree
2017-03-21
Wesley W. Terpstra
configstring: rename variables to dts
commit
|
commitdiff
|
tree
2017-03-21
Wesley W. Terpstra
riscv: remove dependency on num_cores
commit
|
commitdiff
|
tree
2017-03-21
Wesley W. Terpstra
bootrom: include compiled dtb
commit
|
commitdiff
|
tree
2017-03-21
Wesley W. Terpstra
sim: create DTS instead of config string
commit
|
commitdiff
|
tree
2017-03-21
Wesley W. Terpstra
sim: define emulated CPU clock rate to be 1GHz
commit
|
commitdiff
|
tree
2017-03-21
Wesley W. Terpstra
autoconf: put location of 'dtc' into config.h
commit
|
commitdiff
|
tree