projects / gem5.git / search
| 2020-03-13 | Giacomo Travaglini | arch-arm: Fix Arch detection in FS if there is not... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-12 | Adrian Herrera | dev-arm: add FVP Base Power Controller model Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-12 | Adrian Herrera | arch-arm: Rewrite getMPIDR Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-11 | Andriani Mappoura | arch-arm: Correct the Ids and names of the PMU events Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-10 | Giacomo Travaglini | arch-arm: Remove unnecessary RegIndex set for VSTR... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-10 | Adrian Herrera | arch-arm: GenericTimer arch regs, perms/trapping Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-10 | Adrian Herrera | dev-arm: Refactor GenericTimer Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-10 | Giacomo Travaglini | arch-arm: Hint the compiler to inline getArmSystem Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-10 | Giacomo Travaglini | arch-arm: Speedup ARM execution by avoiding expensive... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-10 | Giacomo Travaglini | arch-arm: python3 "/" will always produce a float Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-10 | Giacomo Travaglini | misc: Replace basestring with six.string_types Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-10 | Giacomo Travaglini | misc: Replace __metaclass__ with six.add_metaclass Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-10 | Giacomo Travaglini | misc: string.join has been removed in python3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-10 | Giacomo Travaglini | python: The new module has been removed in python3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-10 | Andreas Sandberg | python: Make meta class declarations Python 3 safe |
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| 2020-03-04 | Giacomo Travaglini | arch-arm: Remove unused getArmSystem helper Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-04 | Timothy Hayes | mem-ruby: Minor Ruby Prefetcher fixes |
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| 2020-03-03 | Giacomo Travaglini | tests: simple_ruby_test's valid_host is X86 only Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-02 | Adrian Herrera | dev-arm: Add missing UARTs (PL011) to VExpress_GEM5... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-02 | Adrian Herrera | dev-arm: Add trusted SP805 to VExpress_GEM5 platform Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-02 | Adrian Herrera | dev-arm: Add trusted SRAM memory to VExpress_GEM5 platform Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-03-02 | Adrian Herrera | dev-arm: Add flash0 memory to VExpress_GEM5 platform Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-28 | Adrian Herrera | dev-arm: PL031, fix AMBA ID and clock names Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-28 | Giacomo Travaglini | learning-gem5: Use zero initialization in hello_goodbye... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-25 | Adrian Herrera | dev-arm: RealView, add support for off-chip memory Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-25 | Adrian Herrera | dev-arm: default _on_chip_memory on RealView Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-20 | Giacomo Travaglini | dev-arm: Fix setupBootloader for VExpress_GEM5_V2 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-19 | Adrian Herrera | arch-arm: ArmISA::clear, inval TLB cached miscregs Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-19 | Adrian Herrera | misc: pass ThreadContext on ISA clear Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-19 | Giacomo Travaglini | cpu: Fix vector renaming bug Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-19 | Giacomo Travaglini | arch, arch-arm: Use BaseISA in RenameMode interface Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-19 | Adrian Herrera | arch-arm: Fix CNTFRQ_EL0 permission bits |
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| 2020-02-17 | Giacomo Travaglini | arch-arm: Be more verbose on load/store construction Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-17 | Giacomo Travaglini | base: Use a int to store fgetc return value Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-17 | Giacomo Travaglini | arch-arm: Fix ArmKVM build Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-17 | Giacomo Travaglini | cpu: Mark ExecContext::tcBase() as const Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-13 | Giacomo Travaglini | ext: Add failure node to JUnit xml file Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-11 | Giacomo Travaglini | tests,misc: update TESTING.md documentation Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-10 | Giacomo Travaglini | tests: hello_se using host tag Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-10 | Giacomo Travaglini | tests: Add --host tag Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-10 | Giacomo Travaglini | configs: Using VExpress_GEM5_V1 as a default for Options.py Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-10 | Giacomo Travaglini | arch-arm: LDTRSW was not marked as unpriviledged Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-06 | Giacomo Travaglini | tests: Move old quick regressions back into their original set Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-04 | Adrian Herrera | arch-arm: AArch64 reg access HCR_EL2.E2H filter Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-04 | Adrian Herrera | arch-arm: reg access permissions highest EL helper Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-02-04 | Giacomo Travaglini | arch-arm: Split translateFs to distinguish when MMU... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-31 | Ciro Santilli | configs: allow fs.py and fs_bigLITTLE.py to work without... Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-31 | Ciro Santilli | configs: fs.py can take multiple disk images on most... Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-31 | Ciro Santilli | config: add --bootloader to fs.py and fs_bigLITTLE.py |
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| 2020-01-31 | Ciro Santilli | dev-arm: add boot_loader param to RealView setupBootLoader Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-27 | Adrian Herrera | system-arm: AArch64 boot, init CNTFRQ_EL0 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-23 | Adrian Herrera | dev-arm: SP805 peripherals in VExpress_GEM5_Base Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-22 | Adrian Herrera | dev-arm: add Watchdog Module SP805 model Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-22 | Adrian Herrera | dev-arm: VExpress_GEM5_Base, add refclock 32KHz Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-22 | Giacomo Travaglini | tests: Fix python line break in m5_exit test Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-21 | Giacomo Travaglini | tests: Add a timeout to getremotetime Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-21 | Adrian Herrera | dev-arm: add FixedClock SimObject Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-21 | Giacomo Travaglini | tests: Adding --bin-path option to select tests bin... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-21 | Giacomo Travaglini | tests: fs/linux/arm passing M5_PATH via commandline Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-17 | Timothy Hayes | configs: MESI_Three_level python parameters |
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| 2020-01-17 | Timothy Hayes | misc: add Arm build_opts for MESI_Three_Level and MOESI_hammer |
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| 2020-01-15 | Adrian Herrera | arch-arm: ELIsInHost, check VHE and SecEL2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-15 | Adrian Herrera | arch-arm: Virtualization Host Extensions checking Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-14 | Adrian Herrera | system-arm: bigLITTLE with VExpress_GEM5_V2 in dtb Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-10 | Adrian Herrera | dev-arm: VExpress_GEM5_Base, fix daughterboard reference Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-09 | Giacomo Travaglini | base, gpu-compute: Move gpu AMOs into the generic header Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-08 | Giacomo Travaglini | arch, base: Move arm AtomicOpFunctor into the generic... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-08 | Giacomo Travaglini | base: Move AtomicOpFunctors to a dedicated header Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-07 | Gabor Dozsa | cpu: Disable O3CPU value forwarding with write strobes |
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| 2020-01-07 | Gabor Dozsa | cpu: Use enums for O3CPU store value forwarding |
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| 2020-01-07 | Giacomo Travaglini | system-arm: GICv2/GICv3 have different Distributor... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-07 | Giacomo Travaglini | system-arm: Rename ARM bootloader source Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-07 | Giacomo Travaglini | system-arm: Rename ARM bootloader directories Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-07 | Adrian Herrera | misc: Reflect changes of arm bootloader name |
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| 2020-01-06 | Adrian Herrera | arch-arm: Semihosting, specify files root dir Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-06 | Michiel van Tol | dev-arm: Fix SMMUv3 walkMasks in page table ops Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-06 | Giacomo Travaglini | dev-arm: Fix SMMUv3 16KB next-level table address masking Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-06 | Adrian Herrera | dev-arm: GICv3, handle GICR_ICFGR0 WI behaviour Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-06 | Adrian Herrera | configs-arm: enable PMU instantiation in CpuCluster Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2020-01-03 | Giacomo Gabrielli | cpu: Fix issue with MinorCPU predicated-false mem.... |
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| 2020-01-03 | Gabor Dozsa | cpu: Disable MinorCPU value forwarding with write strobes |
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| 2019-12-23 | Giacomo Travaglini | tests: Always print stderr in gem5 Fixtures Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-20 | Giacomo Travaglini | configs: arm realview(64) regressions using VExpress_GEM5_V1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-18 | Adrian Herrera | arch-arm: Semihosting, fix SYS_FLEN Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-18 | Adrian Herrera | sim: kernelExtras optional load addresses Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-18 | Adrian Herrera | python: fix "fatal" usage in fdthelper Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-18 | Adrian Herrera | arch-arm: Secure EL2 checking Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-18 | Adrian Herrera | arch-arm: AArch64 trap check, arbitrary ECs/Imms Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-16 | Adrian Herrera | sim: kernelExtras if no kernel provided Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-11 | Giacomo Travaglini | arch-arm: Always initialize SVE memData Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-11 | Giacomo Travaglini | arch-arm: Avoid creating an empty byteEnable vector Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-11 | Giacomo Travaglini | cpu: Replace empty byteEnable check with Request::isMasked Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-11 | Giacomo Travaglini | cpu: Fix coding style (byteEnable->byte_enable) Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-11 | Giacomo Travaglini | cpu: Add byteEnable assertions to readMem and initateMemRead Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Adrian Herrera | dev-arm: GenericTimer, configurable base and low freqs Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Adrian Herrera | dev-arm: GenericTimer, freq as 32-bit value Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Giacomo Travaglini | arch-arm: Disambuiguate NumFloatV7ArchRegs usage Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Giacomo Travaglini | arch-arm: Unify VLdmStm behaviour when reg out of index Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Giacomo Travaglini | arch-arm: Fix NumVecV7ArchRegs value (64->16) Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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| 2019-12-10 | Giacomo Travaglini | arch-arm: Reorder arch/arm/registers.hh constants Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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