soc.git
2019-04-01 Daniel BenusovichAdd SetAssociativeCache source with read logic
2019-04-01 Daniel BenusovichMove read L1 block into the correct location.
2019-04-01 Daniel BenusovichCorrect failing test.
2019-04-01 Daniel BenusovichCorrect missing function call in unit test.
2019-04-01 Daniel BenusovichCorrect comment in TLB
2019-04-01 Daniel BenusovichCorrecting read/write port assignments
2019-03-31 Daniel BenusovichRemove VectorAssembler files
2019-03-31 Daniel BenusovichRemove VectorAssembler from CAM. Thanks Luke
2019-03-26 Luke Kenneth... spelling correction
2019-03-20 Daniel BenusovichAdd PteEntry comments
2019-03-20 Daniel BenusovichUpdate TLB to follow PermissionValidator changes
2019-03-20 Daniel BenusovichUpdate PermissionValidator to use PteEntry Parser to...
2019-03-20 Daniel BenusovichAdd PteEntry parser to centralize Page Table Entry...
2019-03-20 Daniel BenusovichDelete unused resource RegisterFile
2019-03-14 Luke Kenneth... whitespace cleanup
2019-03-14 Daniel BenusovichAdd permission validator unit test. Still needs more...
2019-03-14 Daniel BenusovichAdd valid bit check to permission validator
2019-03-14 Daniel BenusovichAdd missing argument for L1 memory size
2019-03-13 Luke Kenneth... whitespace
2019-03-13 Luke Kenneth... spelling correction
2019-03-13 Luke Kenneth... super is a keyword: replace with "supermode" in TLB...
2019-03-13 Luke Kenneth... move comments to docstring block
2019-03-13 Daniel BenusovichReplace RegisterFile with Memory.
2019-03-13 Daniel BenusovichUpdate comments CAM
2019-03-13 Daniel BenusovichDelete CacheWalker
2019-03-13 Daniel BenusovichDelete RegisterFile
2019-03-12 Luke Kenneth... remove whitespace
2019-03-12 Luke Kenneth... remove whitespace
2019-03-12 Luke Kenneth... remove whitespace
2019-03-12 Daniel BenusovichRemove whitespace
2019-03-12 Daniel BenusovichCorrect misspelled word
2019-03-12 Daniel BenusovichAdd logic to TLB to correctly utilize Cam, RegisterFile...
2019-03-12 Daniel BenusovichRemove whitespace
2019-03-12 Daniel BenusovichUpdate PermissionValidator to actually function. Needs...
2019-03-12 Daniel BenusovichUpdate comments. Remove Whitespace
2019-03-12 Daniel BenusovichAdd RegisterFile class for usage in the TLB.
2019-03-10 Daniel BenusovichShow that read_warning is not necessary. But the line...
2019-03-10 Daniel BenusovichUpdate CAM comments to reflect new usage
2019-03-10 Daniel BenusovichAdd multiple match test
2019-03-10 Daniel BenusovichRemove wen term and shift If blocks to remove NOT need
2019-03-09 Luke Kenneth... whitespace cleanup
2019-03-09 Luke Kenneth... use binary input to test, bit clearer
2019-03-09 Luke Kenneth... rename input variable to in_val (input is a python...
2019-03-09 Luke Kenneth... rename input variable to i (input is a python keyword)
2019-03-09 Luke Kenneth... whitespace (put intermediate on separate line)
2019-03-09 Luke Kenneth... rename input to i (input is a python keyword)
2019-03-09 Luke Kenneth... put inversion of write-enable into its own signal
2019-03-09 Daniel BenusovichChange test vcd output file name to match test filenames
2019-03-09 Daniel BenusovichRemove whitespace
2019-03-09 Daniel BenusovichCorrect comment in Cam to reflect changes
2019-03-09 Daniel BenusovichAdd comments to Cam test
2019-03-09 Daniel BenusovichAdd one more function comment for vector address test
2019-03-09 Daniel BenusovichAdd comments for AddressEncoder and associated tests
2019-03-09 Daniel BenusovichCorrect comments for test_cam_entry
2019-03-09 Daniel BenusovichCorrect comment for vector assembler test
2019-03-09 Daniel BenusovichAdd comments for VectorAssembler
2019-03-09 Daniel BenusovichAdd VectorAssembler to accept match results from CamEnt...
2019-03-09 Daniel BenusovichAdd VectorAssembler to make the graph from yosys beautiful.
2019-03-09 Daniel BenusovichIgnore generate .v files for now at least
2019-03-09 Daniel BenusovichModify Cam to use AddressEncoder instead of two encoders
2019-03-09 Daniel BenusovichCorrect incorrect output bit size
2019-03-09 Daniel BenusovichAdd AddressEncoder to consolidate encoder modules and...
2019-03-09 Daniel BenusovichUpdate assert functions to remove duplicated code via...
2019-03-07 Daniel BenusovichAdd submodule names explicitly for easier yosys graph...
2019-03-06 Daniel BenusovichRemove whitespace
2019-03-06 Daniel BenusovichAdd todo for encoder. To create a new encoder module...
2019-03-06 Daniel BenusovichAdd multiple match check to unit test
2019-03-06 Daniel BenusovichAdd logic for multiple match line.
2019-03-06 Daniel BenusovichRemove WalkingPriorityEncoder. This module is OBE and...
2019-03-05 Luke Kenneth... whoops move comment
2019-03-05 Luke Kenneth... moved code (hardware) which doesnt depend on the index...
2019-03-05 Luke Kenneth... use binary-invert rather than == 0 comparison
2019-03-05 Luke Kenneth... use binary test rather than comparison against 1,
2019-03-05 Luke Kenneth... remove whitespace
2019-03-05 Luke Kenneth... remove whitespace (again)
2019-03-05 Daniel BenusovichUpdate unit test to pass. Needs more testing for multip...
2019-03-05 Daniel BenusovichAdjust main function port declarations
2019-03-05 Daniel BenusovichUpdate CAM to follow Xilinx interface.
2019-03-05 Daniel BenusovichCorrect main of CamEntry
2019-03-05 Daniel BenusovichAdd comma. woops
2019-03-05 Daniel BenusovichUpdate CAM to represent and actual CAM. No more key!
2019-03-05 Daniel BenusovichUpdating CAM entry to actually be a CAM. No key used...
2019-03-04 Luke Kenneth... add Makefile to generate Cam.v verilog
2019-03-04 Luke Kenneth... comments and whitespace cleanup
2019-03-04 Luke Kenneth... comments and whitespace cleanup
2019-03-04 Luke Kenneth... comments and whitespace cleanup
2019-03-04 Luke Kenneth... comments and whitespace cleanup
2019-03-04 Luke Kenneth... comments and whitespace cleanup
2019-03-04 Luke Kenneth... comments and whitespace cleanup
2019-03-04 Luke Kenneth... comments and whitespace cleanup
2019-03-01 Daniel BenusovichAdd unique Priority Encoder to allow for multiple match...
2019-02-25 Daniel BenusovichA few more comments for the src
2019-02-25 Daniel BenusovichAdding Reset. Cleaning Logic for CAM. Still needs tests
2019-02-25 Daniel BenusovichAdd reset logic
2019-02-23 Daniel BenusovichUpdating CAM to (hopefully) full functionality. Needs...
2019-02-23 Daniel BenusovichUpdating CAM so that the submodules actually work....
2019-02-23 Daniel BenusovichAdding more logic to test
2019-02-23 Daniel BenusovichUpdating to elaborate
2019-02-23 Daniel BenusovichUpdating to use assert_eq and assert_ne
2019-02-23 Daniel BenusovichMoving all source scripts
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