gem5.git
2018-07-23 Gabe Blacksystemc: Add stubbed out versions of the sc_time functions.
2018-07-23 Gabe Blacksystemc: Add the sc_nbdefs.hh header from Accellera.
2018-07-23 Gabe Blacksystemc: Add a stub version of the sc_interface class.
2018-07-23 Gabe Blacksystemc: Hook up sc_main.
2018-07-23 Gabe Blacksystemc: Partially implement the sc_module_name class.
2018-07-23 Robert Kovacsicsmem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-20 Robert Kovacsicsmem: Removed "using namespace std;" from src/mem/packet.cc
2018-07-19 Robert Kovacsicsmem: Fix off-by-one error in checkFunctional, and simpl...
2018-07-19 Robert Kovacsicsmem-cache: Typo in comment: 'proceed' -> 'precede'
2018-07-17 Ciro Santillidev, arm: accept and ignore writes to GIC APRn registers
2018-07-16 Gabe Blacksystemc: Add a stub kernel SimObject.
2018-07-16 Gabe Blacksystemc: Add a stubbed out sc_object class.
2018-07-16 Giacomo Travagliniarch-arm: Introduce ARMv8.1 Virtual Timer System Registers
2018-07-16 Giacomo Travagliniarch-arm: Introduce RAS System Registers
2018-07-13 Andreas Sandbergconfigs: Update the DRAM sweep script to use PyTrafficGen
2018-07-13 Andreas Sandbergcpu: Add a Python-enabled traffic generator
2018-07-13 Andreas Sandbergcpu: Support trace termination in BaseTrafficGen
2018-07-13 Andreas Sandbergcpu: Unify error handling for address generators
2018-07-13 Andreas Sandbergcpu: Split the traffic generator into two classes
2018-07-10 Jason Lowe... misc: Fix BaseCPU doxygen
2018-07-09 Robertarch-riscv: enable rudimentary fs simulation
2018-07-09 Austin Harrisarch-riscv: Fix the srlw and srliw instructions.
2018-06-29 Andreas Sandbergbase: Add a M5_PUBLIC and M5_LOCAL attribute macro
2018-06-28 Andreas Sandbergpython: Fix call bug in @cxxMethod when override is...
2018-06-28 Andreas Sandbergcpu: Remove reduntant protobuf includes
2018-06-28 Andreas Sandbergpython: Fixup incorrect syntax in PyBind argument handler
2018-06-28 Andreas Sandbergmem: Add a memory delay simulator
2018-06-28 Andreas Sandbergarch-arm: Fix incorrect t{0,1}sz field in TTBCR
2018-06-28 Giacomo Travaglinibase: Add an asymmetrical Coroutine class
2018-06-26 Alexandru Dutugpu-compute: Remove unneeded Request::setVirt call
2018-06-26 Nikos Nikolerispython: Add support for multiplying proxies to compatib...
2018-06-26 Gabe Blackscons: Generalize building binaries.
2018-06-25 Matt Sinclairsyscall_emul: adding symlink system call
2018-06-25 Matt Sinclairsyscall_emul: adding link system call
2018-06-22 Nikos Nikolerismem-cache: Promote deferred targets on cache clean...
2018-06-22 Nikos Nikolerismem-cache: Promote targets that don't require writable
2018-06-22 Nikos Nikolerismem-cache: Fix promoting of targets that need writable
2018-06-22 Nikos Nikolerismem-cache: Selectively clear downstream pending
2018-06-22 Matteo M. FusiSConstruct: additional message for the error checking...
2018-06-22 Giacomo Travagliniarch-arm: AArch32 execution triggering AArch64 SW Break
2018-06-22 Giacomo Travagliniarch-arm: BadMode checking if corresponding EL is imple...
2018-06-21 Gabe Blackbase: Add a class which encapsulates Fibers.
2018-06-21 Andreas Sandbergsim: Use the canonical way of iterating over a dictionary
2018-06-21 Andreas Sandbergdev-arm: Use recurseDeviceTree instead of custom in...
2018-06-21 Giacomo Travaglinicpu: Fix bug introduced by RequestPtr type change
2018-06-20 Nikos Nikolerisbase: Fix includes in AddrRangeMap header file
2018-06-20 Jason Lowe... mem-cache: Fix TempCacheBlock insert
2018-06-19 Nikos Nikolerismem: Use address range to find the right physical address
2018-06-19 Nikos Nikolerismem: Use address range to find the destination port...
2018-06-19 Gabe Blackmem: Use the caching in the AddrRangeMap class in Physi...
2018-06-19 Gabe Blackmem: Use the caching built into AddrRangeMap in the...
2018-06-19 Gabe Blackbase: Build caching into the AddrRangeMap class
2018-06-19 Nikos Nikolerisbase, mem: Disambiguate if an addr range is contained...
2018-06-19 Nikos Nikolerismem-cache: Fix support for secure blocks in the FALRU...
2018-06-15 Daniel R. Carvalhomem-cache: Initialize CacheBlk data pointer
2018-06-15 Daniel R. Carvalhomem-cache: Forward declare ReplaceableEntry
2018-06-15 Nikos Nikolerisdev-arm: Fix the address range for some I/O devices
2018-06-15 Tuan Tatests,style: add RISC-V assembly tests
2018-06-15 Gabe Blacksim: Add a SimObject python field which overrides the...
2018-06-14 Tuan Tacpu: Prevent suspended TimingSimple CPUs from fetching...
2018-06-14 Tuan Tacpu: add a new instruction type 'Atomic'
2018-06-14 Tuan Taarch: support issuing Atomic Mem Operation (AMO) requests
2018-06-14 Tuan Tabase,mem: Support AtomicOpFunctor in the classic memory...
2018-06-14 Jason Lowe... ruby: Revamp standalone SLICC script
2018-06-14 Giacomo Travagliniarch-arm: Adapting IllegalExecution fault for AArch32
2018-06-14 Giacomo Travagliniarch-arm: Add Illegal Execution flag to PCState
2018-06-14 Giacomo Travagliniarch-arm: Read APSR in User Mode
2018-06-14 Andreas Sandbergsystem-arm: Split the VExpress_GEM5_V1 base dts
2018-06-14 Rohit Kurupdev-arm: Add new VExpress_GEM5_V1_Base Platform
2018-06-14 Andreas Sandbergcpu-minor: Remove redundant thread startup call
2018-06-14 Andreas Sandbergdev-arm: Remove deprecated GIC test interfaces
2018-06-13 Gabe Blacktests: Make "UnitTest"s more like GTest so they can...
2018-06-13 Nikos Nikolerismem-cache: Remove unnecessary cast in SectorTags::findV...
2018-06-13 Giacomo Travagliniarch-arm: Fix missing Request allocation
2018-06-13 Daniel R. Carvalhomem-cache: Insert on block allocation
2018-06-13 Daniel R. Carvalhomem-cache: Make packet const in insertBlock
2018-06-13 Daniel R. Carvalhomem-cache: Create Sector Cache
2018-06-12 Tuan Tatests: add some pthread and std::thread unit tests
2018-06-12 Daniel R. Carvalhoruby: Fix initial weight in weighted LRU
2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
2018-06-11 Giacomo Travaglinimisc: Substitute pointer to Request with aliased RequestPtr
2018-06-08 Daniel R. Carvalhomem-cache: Change Cache block tag check
2018-06-08 Daniel R. Carvalhomem-cache: Use secure bit in findVictim
2018-06-08 Daniel R. Carvalhomem-cache: Move tagsInUse to children
2018-06-08 Daniel R. Carvalhomem-cache: Return evictions along with victims
2018-06-08 Daniel R. Carvalhomem-cache: Use ReplaceableEntry in findBlockBySetAndWay
2018-06-08 Gabe Blacksim: Rename the SimObject cxx_bases field to cxx_extra_...
2018-06-07 Andreas Sandbergdev-arm: Add a VirtIO MMIO device to VExpress_GEM5_V1
2018-06-07 Andreas Sandbergdev-arm: Add a MMIO transport interface for VirtIO
2018-06-07 Andreas Sandbergdev-arm: Add a GIC interrupt adaptor
2018-06-06 Andreas Sandbergarch-arm: Remove dead doingStage2 variable in PT walker
2018-06-06 Andreas Sandbergsystem-arm: Update gem5 timer interrupt specification
2018-06-06 Andreas Sandbergarch-arm: Perform stage 2 lookups using the EL2 state
2018-06-06 Andreas Sandbergarch-arm: Respect EL from translation type
2018-06-06 Andreas Sandbergarch-arm: Fix page size handling when merging stage...
2018-06-06 Andreas Sandbergdev, arm: Add support for HYP & secure timers
2018-06-06 Andreas Sandbergarch-arm: Adjust breakpoint EC depending on source...
2018-06-01 Daniel R. Carvalhomem-cache: Privatize extractSet
2018-06-01 Daniel R. Carvalhomem-cache: Create an address aware TempCacheBlk
2018-06-01 Daniel R. Carvalhomem-cache: Fix secure bit modification
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