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soc.git
2019-04-01
Daniel Benusovich
Correct failing test.
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2019-04-01
Daniel Benusovich
Correct missing function call in unit test.
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2019-04-01
Daniel Benusovich
Correct comment in TLB
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2019-04-01
Daniel Benusovich
Correcting read/write port assignments
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2019-03-31
Daniel Benusovich
Remove VectorAssembler files
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2019-03-31
Daniel Benusovich
Remove VectorAssembler from CAM. Thanks Luke
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2019-03-26
Luke Kenneth...
spelling correction
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2019-03-20
Daniel Benusovich
Add PteEntry comments
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2019-03-20
Daniel Benusovich
Update TLB to follow PermissionValidator changes
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2019-03-20
Daniel Benusovich
Update PermissionValidator to use PteEntry Parser to...
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2019-03-20
Daniel Benusovich
Add PteEntry parser to centralize Page Table Entry...
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2019-03-20
Daniel Benusovich
Delete unused resource RegisterFile
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2019-03-14
Luke Kenneth...
whitespace cleanup
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2019-03-14
Daniel Benusovich
Add permission validator unit test. Still needs more...
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2019-03-14
Daniel Benusovich
Add valid bit check to permission validator
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2019-03-14
Daniel Benusovich
Add missing argument for L1 memory size
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2019-03-13
Luke Kenneth...
whitespace
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2019-03-13
Luke Kenneth...
spelling correction
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2019-03-13
Luke Kenneth...
super is a keyword: replace with "supermode" in TLB...
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2019-03-13
Luke Kenneth...
move comments to docstring block
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2019-03-13
Daniel Benusovich
Replace RegisterFile with Memory.
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2019-03-13
Daniel Benusovich
Update comments CAM
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2019-03-13
Daniel Benusovich
Delete CacheWalker
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2019-03-13
Daniel Benusovich
Delete RegisterFile
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2019-03-12
Luke Kenneth...
remove whitespace
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2019-03-12
Luke Kenneth...
remove whitespace
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2019-03-12
Luke Kenneth...
remove whitespace
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2019-03-12
Daniel Benusovich
Remove whitespace
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2019-03-12
Daniel Benusovich
Correct misspelled word
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2019-03-12
Daniel Benusovich
Add logic to TLB to correctly utilize Cam, RegisterFile...
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2019-03-12
Daniel Benusovich
Remove whitespace
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2019-03-12
Daniel Benusovich
Update PermissionValidator to actually function. Needs...
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2019-03-12
Daniel Benusovich
Update comments. Remove Whitespace
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2019-03-12
Daniel Benusovich
Add RegisterFile class for usage in the TLB.
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2019-03-10
Daniel Benusovich
Show that read_warning is not necessary. But the line...
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2019-03-10
Daniel Benusovich
Update CAM comments to reflect new usage
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2019-03-10
Daniel Benusovich
Add multiple match test
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2019-03-10
Daniel Benusovich
Remove wen term and shift If blocks to remove NOT need
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2019-03-09
Luke Kenneth...
whitespace cleanup
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2019-03-09
Luke Kenneth...
use binary input to test, bit clearer
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2019-03-09
Luke Kenneth...
rename input variable to in_val (input is a python...
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2019-03-09
Luke Kenneth...
rename input variable to i (input is a python keyword)
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2019-03-09
Luke Kenneth...
whitespace (put intermediate on separate line)
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2019-03-09
Luke Kenneth...
rename input to i (input is a python keyword)
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2019-03-09
Luke Kenneth...
put inversion of write-enable into its own signal
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2019-03-09
Daniel Benusovich
Change test vcd output file name to match test filenames
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2019-03-09
Daniel Benusovich
Remove whitespace
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2019-03-09
Daniel Benusovich
Correct comment in Cam to reflect changes
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2019-03-09
Daniel Benusovich
Add comments to Cam test
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2019-03-09
Daniel Benusovich
Add one more function comment for vector address test
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2019-03-09
Daniel Benusovich
Add comments for AddressEncoder and associated tests
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2019-03-09
Daniel Benusovich
Correct comments for test_cam_entry
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2019-03-09
Daniel Benusovich
Correct comment for vector assembler test
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2019-03-09
Daniel Benusovich
Add comments for VectorAssembler
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2019-03-09
Daniel Benusovich
Add VectorAssembler to accept match results from CamEnt...
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2019-03-09
Daniel Benusovich
Add VectorAssembler to make the graph from yosys beautiful.
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2019-03-09
Daniel Benusovich
Ignore generate .v files for now at least
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2019-03-09
Daniel Benusovich
Modify Cam to use AddressEncoder instead of two encoders
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2019-03-09
Daniel Benusovich
Correct incorrect output bit size
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2019-03-09
Daniel Benusovich
Add AddressEncoder to consolidate encoder modules and...
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2019-03-09
Daniel Benusovich
Update assert functions to remove duplicated code via...
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2019-03-07
Daniel Benusovich
Add submodule names explicitly for easier yosys graph...
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2019-03-06
Daniel Benusovich
Remove whitespace
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2019-03-06
Daniel Benusovich
Add todo for encoder. To create a new encoder module...
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2019-03-06
Daniel Benusovich
Add multiple match check to unit test
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2019-03-06
Daniel Benusovich
Add logic for multiple match line.
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2019-03-06
Daniel Benusovich
Remove WalkingPriorityEncoder. This module is OBE and...
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2019-03-05
Luke Kenneth...
whoops move comment
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2019-03-05
Luke Kenneth...
moved code (hardware) which doesnt depend on the index...
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2019-03-05
Luke Kenneth...
use binary-invert rather than == 0 comparison
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2019-03-05
Luke Kenneth...
use binary test rather than comparison against 1,
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2019-03-05
Luke Kenneth...
remove whitespace
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2019-03-05
Luke Kenneth...
remove whitespace (again)
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2019-03-05
Daniel Benusovich
Update unit test to pass. Needs more testing for multip...
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2019-03-05
Daniel Benusovich
Adjust main function port declarations
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2019-03-05
Daniel Benusovich
Update CAM to follow Xilinx interface.
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2019-03-05
Daniel Benusovich
Correct main of CamEntry
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2019-03-05
Daniel Benusovich
Add comma. woops
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2019-03-05
Daniel Benusovich
Update CAM to represent and actual CAM. No more key!
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2019-03-05
Daniel Benusovich
Updating CAM entry to actually be a CAM. No key used...
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2019-03-04
Luke Kenneth...
add Makefile to generate Cam.v verilog
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2019-03-04
Luke Kenneth...
comments and whitespace cleanup
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2019-03-04
Luke Kenneth...
comments and whitespace cleanup
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2019-03-04
Luke Kenneth...
comments and whitespace cleanup
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2019-03-04
Luke Kenneth...
comments and whitespace cleanup
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2019-03-04
Luke Kenneth...
comments and whitespace cleanup
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2019-03-04
Luke Kenneth...
comments and whitespace cleanup
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2019-03-04
Luke Kenneth...
comments and whitespace cleanup
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2019-03-01
Daniel Benusovich
Add unique Priority Encoder to allow for multiple match...
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2019-02-25
Daniel Benusovich
A few more comments for the src
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2019-02-25
Daniel Benusovich
Adding Reset. Cleaning Logic for CAM. Still needs tests
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2019-02-25
Daniel Benusovich
Add reset logic
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2019-02-23
Daniel Benusovich
Updating CAM to (hopefully) full functionality. Needs...
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2019-02-23
Daniel Benusovich
Updating CAM so that the submodules actually work....
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2019-02-23
Daniel Benusovich
Adding more logic to test
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2019-02-23
Daniel Benusovich
Updating to elaborate
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2019-02-23
Daniel Benusovich
Updating to use assert_eq and assert_ne
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2019-02-23
Daniel Benusovich
Moving all source scripts
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2019-02-23
Daniel Benusovich
Moving cam_entry tests
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2019-02-23
Daniel Benusovich
Moving test_cam_entry
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