2022-02-19 |
Luke Kenneth... | put together coldboot startup firmware |
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2022-02-19 |
Luke Kenneth... | hm -abc9 seems to be working, and without -nowidelut |
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2022-02-18 |
Luke Kenneth... | add DRAM class to DDR3Soc |
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2022-02-18 |
Luke Kenneth... | add FPGA argument to DDR3SoC |
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2022-02-18 |
Luke Kenneth... | add microwatt console lib and #includes |
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2022-02-18 |
Luke Kenneth... | make cpu optional (test purposes), make bios optional, |
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2022-02-16 |
Luke Kenneth... | remove minerva cpu |
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2022-02-16 |
Luke Kenneth... | drop clock frequency to 25 mhz and disable abc9 (it... |
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2022-02-16 |
Luke Kenneth... | add openocd load command for ecp5 |
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2022-02-16 |
Luke Kenneth... | wildcards never ok. update comments |
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2022-02-16 |
Luke Kenneth... | add copyright notices |
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2022-02-16 |
Luke Kenneth... | update ECP5 PLL to accept parameters for setting arbitr... |
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2022-02-16 |
Luke Kenneth... | add start of README as reminder |
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2022-02-16 |
Luke Kenneth... | * add uart_pins to UART16550 peripheral so they get... |
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2022-02-16 |
Luke Kenneth... | * disable DDR3 for now |
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2022-02-15 |
Luke Kenneth... | connect up stall signals (fake) for WB Classic compliance |
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2022-02-15 |
Luke Kenneth... | alternative uart wishbone mapping which just takes... |
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2022-02-15 |
Luke Kenneth... | attempt to do 8-bit downconvert on wishbone bus for... |
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2022-02-15 |
Luke Kenneth... | correct syscon bus address to 0xC000_0000 |
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2022-02-15 |
Luke Kenneth... | add microwatt SYSCON peripheral at 0xc000_0000 |
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2022-02-15 |
Luke Kenneth... | increase size of bootmem |
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2022-02-15 |
Luke Kenneth... | add interrupt controller module, remove stall feature... |
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2022-02-15 |
Luke Kenneth... | FLGA_TARGET=verilator not uppercase |
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2022-02-14 |
Luke Kenneth... | add external cpu |
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2022-02-14 |
Luke Kenneth... | convert boot rom to bootmem and get first hello_world... |
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2022-02-14 |
Luke Kenneth... | add IBM microwatt CC4 license and copyright notices |
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2022-02-14 |
Luke Kenneth... | add first cut of verilator simulation, over from microwatt |
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2022-02-14 |
Luke Kenneth... | add verilog build option, make DDR3 PHY optional, add... |
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2022-02-13 |
Luke Kenneth... | add future sim option (needs Simulated DDR PHY) |
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2022-02-13 |
Luke Kenneth... | add build to gitignore |
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2022-02-13 |
Luke Kenneth... | rename examples to src |
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2022-02-13 |
Luke Kenneth... | not for any good reason, separate adding the uart16550... |
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2022-02-13 |
Luke Kenneth... | add MemoryMap to UART16550 (TODO, put that into UART165... |
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2022-02-13 |
Luke Kenneth... | start adding uart16550 |
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2022-02-13 |
Luke Kenneth... | select a firmware file |
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2022-02-13 |
Luke Kenneth... | allow selection of alternative FPGAs at commandline |
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2022-02-13 |
Luke Kenneth... | add blinky lights so we know FPGA is alive |
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2022-02-13 |
Luke Kenneth... | make firmware and cpu optional for now to get a basic... |
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2022-02-12 |
Luke Kenneth... | begin a tidyup on the example |
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2022-02-10 |
Luke Kenneth... | resolve imports, whitespace, add Copyright |
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2022-02-10 |
Luke Kenneth... | add crg.py |
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2022-02-10 |
Luke Kenneth... | update contributors |
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2022-02-10 |
Luke Kenneth... | sort out license and headers for NLnet and NGI POINTER... |
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2022-02-10 |
Luke Kenneth... | add gram soc example and license and contributors |
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2022-02-09 |
Luke Kenneth... | empty first commit |
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