2022-09-17 |
Luke Kenneth... | add vec2/3/4 test_pysvp64dis test |
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2022-09-16 |
Luke Kenneth... | comments on test_9_fptrans |
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2022-09-16 |
Dmitry Selyutin | test_power_decoder: mark minor_19.csv as opint |
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2022-09-16 |
Dmitry Selyutin | test_pysvp64dis: test fptrans |
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2022-09-16 |
Dmitry Selyutin | selectable_int: replace bit_count with bit_length |
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2022-09-16 |
Dmitry Selyutin | sv_binutils_fptrans: adopt script for reuse |
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2022-09-16 |
Dmitry Selyutin | power_insn: postpone updating per-instruction operands |
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2022-09-15 |
Dmitry Selyutin | power_insn: perform faster PPC database lookups |
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2022-09-15 |
Dmitry Selyutin | sv_binutils_fptrans: fix disassembly |
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2022-09-15 |
Dmitry Selyutin | sv_binutils_fptrans: fptrans binutils generator |
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2022-09-15 |
Dmitry Selyutin | power_insn: support instruction bytes conversion |
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2022-09-15 |
Dmitry Selyutin | selectable_int: allow setting multiple bit |
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2022-09-15 |
Dmitry Selyutin | power_insn: allow accessing instruction bits |
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2022-09-15 |
Luke Kenneth... | add minor_4.csv for maddld/maddhdu/maddhd and to insn_d... |
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2022-09-15 |
Luke Kenneth... | fix sprset mtspr/mfspr pseudocode with wrong definition of |
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2022-09-14 |
Jacob Lifshay | add svp64 fptrans tests |
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2022-09-14 |
Jacob Lifshay | include *all* fprs/gprs/cr-fields in SimState |
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2022-09-14 |
Jacob Lifshay | fix sv_analysis for fpown and frootn |
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2022-09-14 |
Jacob Lifshay | fix some typos |
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2022-09-13 |
Dmitry Selyutin | power_insn: support signed operands |
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2022-09-13 |
Dmitry Selyutin | power_insn: support branch RM |
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2022-09-13 |
Dmitry Selyutin | power_insn: support CR RM |
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2022-09-13 |
Dmitry Selyutin | power_enums: convert SVExtra to RegType |
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2022-09-13 |
Dmitry Selyutin | power_insn: refactor RM mapping |
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2022-09-13 |
Dmitry Selyutin | sv_binutils: support multiple opcodes; minor fixes |
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2022-09-13 |
Luke Kenneth... | correct assrmbler in test_pysvpy4dis.py |
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2022-09-13 |
Jacob Lifshay | fix X-FORM lines for fptrans -- I forgot Rc |
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2022-09-13 |
Jacob Lifshay | add missing X-FORM lines for fptrans |
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2022-09-13 |
Jacob Lifshay | add comment that fptrans test cases output values are... |
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2022-09-13 |
Jacob Lifshay | add new fptrans unit tests |
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2022-09-13 |
Jacob Lifshay | add fptrans support to isa caller |
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2022-09-13 |
Jacob Lifshay | add fp support to TestRunnerBase |
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2022-09-13 |
Luke Kenneth... | add first pack/unpack to ISACaller |
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2022-09-13 |
Luke Kenneth... | add setter/getter properties to SVP64State, minor code... |
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2022-09-13 |
Luke Kenneth... | remove pack/unpack from SVP64RMModeDecode, it is now... |
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2022-09-13 |
Luke Kenneth... | add batch of instructions from |
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2022-09-12 |
Luke Kenneth... | add hack overloaded meaning of destwid to be pack/unpack. |
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2022-09-12 |
Dmitry Selyutin | power_insn: refactor RM mapping |
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2022-09-12 |
Dmitry Selyutin | sv_binutils: support multiple opcodes; minor fixes |
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2022-09-12 |
Dmitry Selyutin | power_insn: call sv_spec_leave unconditionally |
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2022-09-12 |
Dmitry Selyutin | power_enums: consider CRIn2Sel |
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2022-09-12 |
Dmitry Selyutin | power_insn: fix RCOE check |
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2022-09-12 |
Dmitry Selyutin | power_insn: introduce pseudo cr_in2 |
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2022-09-12 |
Dmitry Selyutin | power_enums: strict selectors conversion |
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2022-09-12 |
Dmitry Selyutin | power_insn: fix typo |
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2022-09-12 |
Dmitry Selyutin | power_insn: support BRANCH and CR mode stubs |
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2022-09-12 |
Dmitry Selyutin | power_insn: refactor register operands |
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2022-09-12 |
Jacob Lifshay | add pseudocode for all fptrans ops |
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2022-09-12 |
Jacob Lifshay | add fptrans helpers, switching existing uses to new... |
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2022-09-12 |
Luke Kenneth... | add hphint and pack/unpack into SVSTATE SPR layout |
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2022-09-12 |
Jacob Lifshay | add fptrans ops to src/openpower/sv/trans/svp64.py |
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2022-09-12 |
Jacob Lifshay | add rest of new fptrans ops to CSVs |
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2022-09-12 |
Luke Kenneth... | remove pack/unpack - now part of sv.setvl |
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2022-09-12 |
Luke Kenneth... | add rudimentary sv.setvl unit test to just check that... |
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2022-09-12 |
Luke Kenneth... | add sv.setvl to instructions as a major hack |
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2022-09-12 |
Luke Kenneth... | split out setvl from sv.setvl test in test_pysvp64dis.py |
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2022-09-12 |
Luke Kenneth... | add extra tests "add." "addo" etc. to test_pysvp64dis.py |
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2022-09-12 |
Luke Kenneth... | demo that "setvl." is not reconstructed with Rc=1 mode |
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2022-09-12 |
Luke Kenneth... | some weird moving of opcodes around, probably because... |
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2022-09-12 |
Luke Kenneth... | skip addpcis for now, needs properly qualifying |
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2022-09-12 |
Jacob Lifshay | fix svanalysis failing due to missing comma in addpcis... |
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2022-09-11 |
Luke Kenneth... | add new CRIn2Sel for later, for getting rid of CRInSel... |
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2022-09-11 |
Luke Kenneth... | BFT does not exist |
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2022-09-11 |
Luke Kenneth... | add sv.isel 12,2,3,*99 test to test_pysvp64dis.py |
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2022-09-11 |
Luke Kenneth... | add some CR3 pysvp64dis.py tests, sv.crand |
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2022-09-11 |
Dmitry Selyutin | power_insn: check exact matches directly in set |
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2022-09-11 |
Dmitry Selyutin | power_insn: group opcodes and names |
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2022-09-11 |
Luke Kenneth... | add sv.isel asm-disasm tests to test_pysvp64dis.py |
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2022-09-11 |
Luke Kenneth... | add missing addpcis to power_enums.py and minor_19.csv |
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2022-09-11 |
Luke Kenneth... | convert minor_19 to bitpattern (for adding addpcis) |
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2022-09-11 |
Luke Kenneth... | whoops lsbshf=2 for CR5 |
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2022-09-11 |
Luke Kenneth... | whoops missed lsb-shift parameter |
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2022-09-11 |
Luke Kenneth... | add comments into CR5Operand class |
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2022-09-11 |
Luke Kenneth... | add CR5Operand and CR3Operand to power_insns.py |
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2022-09-10 |
Luke Kenneth... | huhn? addpcis converts to .long? huhn? |
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2022-09-10 |
Luke Kenneth... | fix issue with pysvp64dis.py load() reading from stdin |
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2022-09-10 |
Dmitry Selyutin | power_insn: perform minor opcodes cleanup |
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2022-09-10 |
Dmitry Selyutin | power_insn: hopefully final take on the opcodes |
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2022-09-10 |
Dmitry Selyutin | power_insn: yet another take on the opcodes |
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2022-09-10 |
Luke Kenneth... | whitespace cleanup |
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2022-09-10 |
Luke Kenneth... | add quine-mckluskey algorithm |
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2022-09-10 |
Dmitry Selyutin | power_insn: refactor register verbose assembly |
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2022-09-10 |
Dmitry Selyutin | power_insn: support pcode |
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2022-09-10 |
Dmitry Selyutin | power_insn: tune TargetAddrOperand disassembly |
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2022-09-10 |
Dmitry Selyutin | power_insn: support CR remap |
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2022-09-10 |
Dmitry Selyutin | power_insn: support non-zero operands |
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2022-09-10 |
Dmitry Selyutin | power_insn: simplify operand naming conventions |
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2022-09-10 |
Dmitry Selyutin | power_insn: drop redundant dataclass incantations |
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2022-09-10 |
Dmitry Selyutin | power_insn: do not print blob suffix unless needed |
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2022-09-10 |
Dmitry Selyutin | power_insn: do not panic upon database query |
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2022-09-10 |
Dmitry Selyutin | power_insn: refactor opcode matching |
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2022-09-10 |
Dmitry Selyutin | power_insn: support D operand in DX form |
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2022-09-10 |
Dmitry Selyutin | power_insn: refactor span detection |
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2022-09-10 |
Dmitry Selyutin | power_insn: simplify code |
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2022-09-10 |
Dmitry Selyutin | power_insn: remove redundant code |
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2022-09-10 |
Dmitry Selyutin | power_insn: decouple extra merge routine |
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2022-09-10 |
Dmitry Selyutin | power_insn: rename extra to spec |
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2022-09-10 |
Dmitry Selyutin | power_insn: deprecate redundant else section |
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2022-09-10 |
Dmitry Selyutin | power_insn: rename Extra classes |
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2022-09-10 |
Dmitry Selyutin | fields.text: this fish ain't moving |
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next |