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riscv-isa-sim.git
2018-09-24
Luke Kenneth...
remove unneeded use of AM_CONDITIONAL
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2018-09-24
Luke Kenneth...
add #define for SPIKE_SIMPLEV, re-run autoreconf
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2018-09-24
Luke Kenneth...
create #defines from identified registers, per opcode
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2018-09-24
Luke Kenneth...
clarify docstring on id_regs.py
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2018-09-24
Luke Kenneth...
add function identifying the registers in each emulated...
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2018-09-24
Luke Kenneth...
identify instructions, plan: extract registers
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2018-09-13
Andrew Waterman
Update README
master
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2018-09-06
Tim Newsome
Merge pull request #235 from riscv/sba
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2018-09-05
Tim Newsome
Fix cut-and-paste bug in 64-bit SBA loads.
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2018-08-24
Andrew Waterman
Handle spike-dasm inputs with leading 0x correctly
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2018-08-24
Tim Newsome
Add dummy custom debug registers, to test OpenOCD....
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2018-08-24
Andrew Waterman
Fix several disassembler bugs
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2018-08-23
Andrew Waterman
Add --disable-dtb option to suppress writing the DTB...
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2018-08-22
Andrew Waterman
Make IRQ_COP read-only/undelegable unless coprocessor...
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2018-08-21
Andrew Waterman
Instantiate disassembler after max_xlen is known
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2018-08-18
Andrew Waterman
Don't increment instret immediately after it is written...
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2018-08-10
Tim Newsome
Fix 2 trigger corner cases. (#229)
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2018-07-31
Andrew Waterman
Make sstatus.MXR readable
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2018-07-23
SeungRyeol Lee
Fix using the uninitialized disassemble object. (#220)
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2018-07-10
Andrew Waterman
Refactor and fix LR/SC implementation (#217)
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2018-06-12
Tim Newsome
Merge pull request #212 from riscv/hartsel
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2018-06-11
Tim Newsome
Update debug_defines.h
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2018-05-31
Andy Wright
Put simif_t declaration in its own file. (#209)
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2018-05-18
Prashanth Mundkur
Fix install of missed header. (#207)
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2018-05-18
Prashanth Mundkur
Extract out device-tree generation and compilation...
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2018-05-04
Andrew Waterman
Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"
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2018-05-04
Andrew Waterman
C.LWSP and C.LDSP with rd=0 are legal instructions
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2018-05-01
Andrew Waterman
Fix commit log for serializing instructions
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2018-04-30
Andrew Waterman
Only break out of the simulator loop on WFI, not on...
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2018-04-29
Andrew Waterman
When no arguments are passed, print spike help, not...
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2018-04-05
Prashanth Mundkur
Allow querying the mmu configuration chosen during...
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2018-04-04
Andrew Waterman
Revert "Fix for issue #183: No illegal instruction...
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2018-03-30
Palmer Dabbelt
Merge pull request #189 from pmundkur/pm-csr-name-api
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2018-03-26
Prashanth Mundkur
Add an api to get the name for a CSR.
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2018-03-22
Andrew Waterman
Implement Hauser misa.C misalignment proposal (#187)
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2018-03-21
Prashanth Mundkur
Fix the access exception during page-table walks to...
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2018-03-19
Tim Newsome
Fix spike-dasm. (#184)
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2018-03-19
Tim Newsome
Merge pull request #182 from riscv/reset_bits
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2018-03-16
Tim Newsome
Implement debug havereset bits
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2018-03-16
Andrew Waterman
Merge branch 'deepsrc-b_fix_issue183'
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2018-03-16
Shubhodeep...
Fix for issue #183: No illegal instruction exception...
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2018-03-14
Prashanth Mundkur
Fix a bug caused by moving misa into state_t. (#180)
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2018-03-13
Prashanth Mundkur
Move processor.isa to state.misa, since it really belon...
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2018-03-10
Tim Newsome
Fix single stepping csrrw instructions (#178)
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2018-03-08
Tim Newsome
Merge pull request #177 from riscv/debug_auth
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2018-03-06
Prashanth Mundkur
Narrow the interface used by the processors and memory...
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2018-03-06
Prashanth Mundkur
Fix install of a missed header from debug_rom.
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2018-03-06
Prashanth Mundkur
Fix a missed header file in the softfloat include install.
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2018-03-03
Andrew Waterman
Implement clearing-misa.C-while-PC-is-misaligned proposal
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2018-03-03
Andrew Waterman
Enforce 2-byte alignment of mepc/sepc/dpc
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2018-03-01
Tim Newsome
Merge pull request #173 from riscv/no_progbuf3
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2018-02-27
Tim Newsome
Add debug module authentication.
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2018-02-21
Andrew Waterman
Don't allow 32-bit instructions to take up multiple...
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2018-02-19
Tim Newsome
Merge pull request #171 from riscv/sysbusbits
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2018-02-19
Tim Newsome
Passes smoke tests with --progsize=0
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2018-02-19
Tim Newsome
WIP. Doesn't work.
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2018-02-13
Andrew Waterman
Implement cycleh/instreth CSRs for RV32 (#172)
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2018-02-01
Tim Newsome
Add --debug-sba option
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2018-01-29
Tim Newsome
Update debug_defines
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2018-01-18
Tim Newsome
Support debug system bus access.
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2018-01-09
Tim Newsome
Use new debug_defines.h.
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2018-01-09
Jonathan Neuschäfer
mem_t: Throw an error if zero-sized memory is requested...
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2018-01-03
Andrew Waterman
Add some missing RVC instructions to disassembler
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2017-12-18
Tim Newsome
Merge pull request #165 from riscv/small_progbuf
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2017-12-11
Tim Newsome
Update debug_defines to latest version.
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2017-12-11
Tim Newsome
Set impebreak.
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2017-12-11
Tim Newsome
Update to latest debug_defines.h.
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2017-12-11
Tim Newsome
Make progbuf a run-time option.
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2017-11-27
Andrew Waterman
Rename badaddr to tval
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2017-11-27
Andrew Waterman
Rename sptbr to satp
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2017-11-27
Andrew Waterman
Set tval to 0 on traps with no specified tval
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2017-11-20
Andrew Waterman
Implement priv-1.11 interrupt-priority scheme (#161)
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2017-11-20
Christopher...
Fix commitlog. (#162)
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2017-11-16
Andrew Waterman
Merge pull request #156 from p12nGH/noncontiguous_harts
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2017-11-15
Gleb Gagarin
hartids knob description added
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2017-11-15
Gleb Gagarin
Support for non-contiguous hartids
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2017-11-10
Andrew Waterman
Remove redundant U/S mode advertisement
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2017-11-10
Andrew Waterman
H-mode no longer exists
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2017-11-10
Andrew Waterman
MPP is now WARL
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2017-11-06
Kito Cheng
Implement Q extension for disassembler (#153)
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2017-11-04
Andrew Waterman
Fix disassembly of c.li 0
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2017-11-03
Palmer Dabbelt
Merge pull request #151 from riscv/htif_dts
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2017-11-03
Palmer Dabbelt
Put HTIF in the device tree
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2017-11-03
Andrew Waterman
Mask medeleg correctly
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2017-11-02
Andrew Waterman
Don't permit delegation of interrupts that M-mode shoul...
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2017-10-20
Andrew Waterman
Fix commit-log for Q extension, and for RV32 (#143)
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2017-10-19
Evan Cox
Fix bus_t bug with devices at 0x0
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2017-10-19
Andrew Waterman
Fix implementation of FMIN/FMAX NaN case
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2017-10-15
jar
Include math.h for NAN (#137)
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2017-10-11
Andrew Waterman
Merge pull request #129 from riscv/q-extension
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2017-09-28
Andrew Waterman
Implement Q extension
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2017-09-25
Tim Newsome
Merge pull request #128 from riscv/reset
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2017-09-25
Andrew Waterman
Update SoftFloat
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2017-09-21
Tim Newsome
Actually let hartreset be set.
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2017-09-21
Tim Newsome
Fix debug reset.
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2017-09-21
Tim Newsome
Fix corner case in repeated execution (#127)
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2017-09-21
Tim Newsome
Fix comment typo. (#126)
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2017-09-12
Tim Newsome
Merge pull request #123 from riscv/debug_interrupts
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2017-09-12
Tim Newsome
Don't take interrupts while in Debug Mode.
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2017-08-28
Tim Newsome
Merge pull request #121 from riscv/debug_store
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