ls2.git
2022-03-31 Luke Kenneth... reduce number of params obtained on QSPI for icarus sim
2022-03-31 Luke Kenneth... got icarus verilog model of QSPI working and it returns...
2022-03-31 Luke Kenneth... whitespace cleanup
2022-03-31 Raptor Engineering... Fix Tercel QSPI master connections
2022-03-31 Luke Kenneth... remove {err} feature from Tercel
2022-03-29 Luke Kenneth... add err wishbone feature to Tercel
2022-03-29 Luke Kenneth... add config-dump from SPI
2022-03-29 Luke Kenneth... remove clk from spi_flash,
2022-03-29 Luke Kenneth... add qspi module to arty_a7
2022-03-29 Luke Kenneth... quick-and-dirty QSPI read test
2022-03-29 Luke Kenneth... use nmigen_boards naming conventions for SPIFlash
2022-03-29 Luke Kenneth... update comments, link/setup of peripherals
2022-03-29 Luke Kenneth... add TODO comments about using platform.add_resources
2022-03-29 Luke Kenneth... whitespace cleanup, 80 char limit
2022-03-29 Luke Kenneth... add patch for n25q to fix model using fork/join, should...
2022-03-29 Raptor Engineering... Add initial integration for OpenCores 10/100 Ethernet MAC
2022-03-28 Raptor Engineering... Fix instructions in comment
2022-03-28 Luke Kenneth... quick memory test increasing by power-2 each time shows...
2022-03-27 Luke Kenneth... set reset from ResetSignal not straight to 1 for HyperRAM
2022-03-27 Luke Kenneth... try latency of 7 for winbond hyperram
2022-03-27 Luke Kenneth... add link to Winbond HyperRAM model
2022-03-27 Luke Kenneth... set upper CSns on HyperRAM to zero and set reset_n HI
2022-03-26 Luke Kenneth... add clock output on hyperram sim
2022-03-26 Luke Kenneth... add all 4 CSn lines for Quad HyperRAM PMOD
2022-03-26 Luke Kenneth... grr
2022-03-26 Luke Kenneth... reduce power-on-delay bits to 2 for icarus sim ecp5
2022-03-26 Luke Kenneth... remove switches from hyperram iverilog test
2022-03-26 Luke Kenneth... remove unneeded model variable
2022-03-26 Luke Kenneth... add missing ECP5 model OBZ.v and rename testbench
2022-03-26 Luke Kenneth... sort out platform IO pads for iverilog hyperram sim
2022-03-26 Luke Kenneth... add hyperram iverilog runner including s27kl0641.v...
2022-03-25 Luke Kenneth... rename ECP5 CRG, move source, remove duplicate version
2022-03-25 Luke Kenneth... up arty a7 frequency to 40 mhz
2022-03-25 Luke Kenneth... increase time for power-on-delay to 2^25 in ECP5
2022-03-25 Luke Kenneth... loop-test on hyperram read/write which needs carriage...
2022-03-24 Luke Kenneth... increase delay on ECP5 ulx3s
2022-03-24 Luke Kenneth... check ulx3s, add CRG support for ulx3s
2022-03-24 Luke Kenneth... establish power-on reset stabilisation for Arty A7...
2022-03-22 Luke Kenneth... add hack to modify VERSA_ECP5 85F platform to speed...
2022-03-22 Luke Kenneth... adding hyperram for arty a7 and also adding a workaroun...
2022-03-20 Luke Kenneth... add microwatt hello_world source
2022-03-20 Luke Kenneth... crank A7 FPGA speed down to experiment
2022-03-20 Luke Kenneth... code-comments
2022-03-20 Luke Kenneth... fix Arty A7-100t PLL with quick demo
2022-03-20 Luke Kenneth... first cut at Arty A7 Clock-Reset-Generator with S7 PLL
2022-03-20 Luke Kenneth... beginnings of arty a7 clock-reset-generator
2022-03-19 Luke Kenneth... add VERSA_ECP5 85F custom board
2022-03-19 Luke Kenneth... move quick read/write test for hyperram in coldboot.c
2022-03-19 Luke Kenneth... set IO_TYPE 3.3v attribute on HyperRAM not IOSTANDARD
2022-03-19 Luke Kenneth... correct pin names for HyperRAMResource, indent spi0...
2022-03-19 Luke Kenneth... fixed hyperram pin names which was stopping verilator...
2022-03-19 Luke Kenneth... disable hyperram for now (under investigation)
2022-03-19 Luke Kenneth... adding in hyperram peripheral
2022-03-18 Luke Kenneth... whitespace / module-import / comments / tidyup
2022-03-18 Luke Kenneth... beginning to add hyperram module
2022-03-18 Luke Kenneth... whitespace cleanup and make SPI core (temporarily)...
2022-03-17 Luke Kenneth... work-in-progress on DDR3 firmware. sigh
2022-03-17 Luke Kenneth... comment about icarus verilog to speed up simulations
2022-03-16 Raptor Engineering... Add initial Tercel SPI controller
2022-03-10 Luke Kenneth... sigh gramWishbone is not WB4-pipeline-burst-compliant
2022-03-09 Luke Kenneth... fix WB6to32 downconverter with stall signalling
2022-03-09 Luke Kenneth... add stall signal to arbiter, assume nmigen-soc takes
2022-03-04 Luke Kenneth... add experimental stall-capable 64-to-32 wishbone converter
2022-03-02 Luke Kenneth... lots of comments in the yosys script file
2022-03-02 Luke Kenneth... invert reset and chip-select on dram, and initialise...
2022-03-02 Luke Kenneth... forgot to include firmware in build for new icarus...
2022-03-01 Luke Kenneth... add new icarus-versa-ecp5 platform in ls2.py
2022-02-28 Luke Kenneth... increase timescale of icarus simulation
2022-02-28 Luke Kenneth... fix undefined uart_tx in icarus simulation, icarus...
2022-02-28 Luke Kenneth... use a slightly different yosys initialisation sequence...
2022-02-28 Luke Kenneth... fix memory issue in yosys synth for icarus
2022-02-28 Luke Kenneth... add icarus simulation of ls2 with DDR3 and ECP5 models
2022-02-23 Luke Kenneth... invert CRG reset on PLL see if it makes any difference
2022-02-23 Luke Kenneth... add comments about DRAM sync clock being identical...
2022-02-22 Luke Kenneth... xdr=4 missing on ddr3 platform request for VERSA_ECP5
2022-02-21 Luke Kenneth... lengthen cdelay pauses by a factor of 10
2022-02-21 Luke Kenneth... * use readl and writel for accessing memory
2022-02-21 Luke Kenneth... use microwatt mmu powerpc.lds with better stack space
2022-02-20 Luke Kenneth... fix dfi initialisation and calibration to use
2022-02-20 Luke Kenneth... set RAM base to #defined DRAM_BASE not hard-coded value
2022-02-20 Luke Kenneth... for simulatio keep the simulated dram in the
2022-02-20 Luke Kenneth... add fake (sim) DRAM from gram library
2022-02-19 Luke Kenneth... match up dram initialisation parameters
2022-02-19 Luke Kenneth... put together coldboot startup firmware
2022-02-19 Luke Kenneth... hm -abc9 seems to be working, and without -nowidelut
2022-02-18 Luke Kenneth... add DRAM class to DDR3Soc
2022-02-18 Luke Kenneth... add FPGA argument to DDR3SoC
2022-02-18 Luke Kenneth... add microwatt console lib and #includes
2022-02-18 Luke Kenneth... make cpu optional (test purposes), make bios optional,
2022-02-16 Luke Kenneth... remove minerva cpu
2022-02-16 Luke Kenneth... drop clock frequency to 25 mhz and disable abc9 (it...
2022-02-16 Luke Kenneth... add openocd load command for ecp5
2022-02-16 Luke Kenneth... wildcards never ok. update comments
2022-02-16 Luke Kenneth... add copyright notices
2022-02-16 Luke Kenneth... update ECP5 PLL to accept parameters for setting arbitr...
2022-02-16 Luke Kenneth... add start of README as reminder
2022-02-16 Luke Kenneth... * add uart_pins to UART16550 peripheral so they get...
2022-02-16 Luke Kenneth... * disable DDR3 for now
2022-02-15 Luke Kenneth... connect up stall signals (fake) for WB Classic compliance
2022-02-15 Luke Kenneth... alternative uart wishbone mapping which just takes...
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