2020-11-13 |
whitequark | vendor.quicklogic: write OpenOCD scripts as part of... |
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2020-11-10 |
whitequark | build.plat: TemplatedPlatform.iter_extra_files→Platform... |
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2020-11-09 |
awygle | hdl.rec: proxy operators correctly. |
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2020-11-06 |
Konrad Beckmann | vendor.intel: add support for Cyclone V internal oscillator |
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2020-11-06 |
whitequark | hdl.ast: deprecate UserValue in favor of ValueCastable. |
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2020-11-06 |
whitequark | sim.pysim: avoid redundant VCD updates. |
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2020-11-06 |
whitequark | examples: clean up oudated code. |
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2020-11-06 |
whitequark | Fix commit 8313d6e7. |
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2020-11-06 |
whitequark | cli: update deprecated import. |
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2020-11-06 |
whitequark | CI: add CPython 3.9 to test matrix. |
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2020-11-06 |
whitequark | CI: run testsuite with -Werror. |
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2020-11-06 |
whitequark | vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_... |
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2020-11-06 |
awygle | hdl.rec: migrate Record from UserValue to ValueCastable. |
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2020-11-06 |
awygle | hdl.ast: implement ValueCastable. |
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2020-11-05 |
whitequark | vendor.quicklogic: part→package |
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2020-11-03 |
Norbert Braun | vendor.xilinx_7series: byte swap generated bitstream |
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2020-11-03 |
Jaro Habiger | lib.fifo: fix {r,w}_level in AsyncFIFOBuffered |
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2020-11-03 |
Jaro Habiger | lib.fifo: fix level on fifo full |
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2020-11-02 |
David Lattimore | vendor.lattice_ice40: zero-pad CLKHF_DIV in SB_HFOSC... |
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2020-10-30 |
Jan Kowalewski | vendor.quicklogic: utilize internal SoC clock in EOS-S3 |
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2020-10-30 |
Jan Kowalewski | vendor.quicklogic: fix toolchain nomenclature |
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2020-10-28 |
Robin Ole Heinemann | lib.fifo.AsyncFFSynchronizer: check input and output... |
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2020-10-27 |
Ben Newhouse | setup: link to latest docs if VCS information is not... |
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2020-10-26 |
whitequark | build.dsl: clean up inversion logic. |
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2020-10-25 |
whitequark | back.{verilog,rtlil}: adjust $verilog_initial_trigger... |
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2020-10-25 |
whitequark | CI: disable codecov project status. |
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2020-10-24 |
anuejn | lib.fifo.AsyncFIFO: fix incorrect latency of r_level. |
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2020-10-22 |
anuejn | tests: make spec directory name unique per test method. |
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2020-10-22 |
whitequark | sim._pyrtl: sign extend RHS of assignment. |
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2020-10-22 |
whitequark | hdl.dsl: error on Elif immediately nested in an If. |
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2020-10-19 |
Jan Kowalewski | vendor.quicklogic: fix syntax |
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2020-10-19 |
Xiretza | setup.py: Exclude "tests" package |
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2020-10-18 |
Xiretza | hdl.ir: Update error message for Instance arguments |
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2020-10-15 |
whitequark | README: Quicklogic EOS S3 is now supported. |
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2020-10-15 |
whitequark | CI: fix code coverage collection. |
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2020-10-15 |
Jan Kowalewski | vendor.quicklogic: new platform. |
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2020-10-15 |
whitequark | tests: keep comments up to date. NFC. |
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2020-10-15 |
whitequark | build.plat: avoid type confusion in _check_feature. |
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2020-09-17 |
Jean-François... | hdl.mem: document ReadPort and WritePort. |
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2020-08-29 |
William D.... | vendor.lattice_{ecp5,machxo_2_3l}: explain how to set... |
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2020-08-27 |
whitequark | setup: synchronize builtin-yosys dependency. |
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2020-08-27 |
whitequark | back.verilog: use `proc -nomux` if it is available. |
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2020-08-27 |
whitequark | sim: split into base, core, and engines. |
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2020-08-27 |
whitequark | sim.pysim: in write_vcd(), close files if an exception... |
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2020-08-27 |
whitequark | sim._pyclock: new type of process. |
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2020-08-27 |
whitequark | sim._pycoro: make src_loc() more robust. |
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2020-08-27 |
whitequark | _toolchain.cxx: work around PyPy missing LDCXXSHARED... |
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2020-08-27 |
whitequark | _toolchain.cxx: new toolchain. |
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2020-08-27 |
whitequark | hdl.ast: clarify exception message for out of bounds... |
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2020-08-27 |
whitequark | nmigen.test.utils: restore FHDLTestCase to gracefully... |
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2020-08-27 |
whitequark | tests: move out of the main package. |
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2020-08-26 |
William D.... | build.run: implement SSH remote builds using Paramiko. |
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2020-08-26 |
whitequark | back.rtlil: do not squash empty modules. |
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2020-08-26 |
whitequark | back.verilog: omit Verilog initial trigger only if... |
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2020-08-26 |
whitequark | vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVIC... |
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2020-08-26 |
whitequark | vendor.xilinx_7series: unbreak. |
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2020-08-26 |
whitequark | sim._pyrtl: optimize uses of reflexive operators. |
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2020-08-26 |
whitequark | back.cxxrtl: actualize Yosys version requirement. |
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2020-08-26 |
whitequark | hdl.ast: avoid unnecessary sign padding in ArrayProxy. |
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2020-08-26 |
whitequark | sim._pyrtl: fix miscompilation of -(Const(0b11, 2)... |
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2020-08-26 |
whitequark | lib.cdc: in AsyncFFSynchronizer(), rename domain= to... |
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2020-08-24 |
Robin Ole Heinemann | vendor.lattice_machxo_2_3l: add SRAM svf generation |
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2020-08-24 |
Mariusz Glebocki | vendor: Add initial support for Symbiflow for Xilinx... |
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2020-08-24 |
Mariusz Glebocki | vendor.xilinx_7series: add `_part` property getter |
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2020-08-22 |
Xiretza | cli: Improve help texts |
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2020-08-15 |
whitequark | docs/lang: use less confusing placeholder variable... |
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2020-08-15 |
awygle | lib.fifo: add `r_level` and `w_level` to all FIFOs |
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2020-08-13 |
whitequark | Add Linguist tags to .gitattributes. |
commit | commitdiff | tree |
2020-08-10 |
Robin Ole Heinemann | vendor.lattice_{ecp5,machxo_2_3l}: specify impl-dir... |
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2020-07-31 |
whitequark | build,vendor: never carry around parts of differential... |
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2020-07-31 |
whitequark | vendor.xilinx_{7series,ultrascale}: use BUFGCTRL rather... |
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2020-07-30 |
Adam Greig | hdl.mem: cast reset value for transparent read ports... |
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2020-07-28 |
Jean THOMAS | nmigen.lib.scheduler: add RoundRobin. |
commit | commitdiff | tree |
2020-07-28 |
Jacob Graves | tests: fix remove unnecessary workaround for some unitt... |
commit | commitdiff | tree |
2020-07-23 |
whitequark | vendor.xilinx_{7series,ultrascale}: add SIM_DEVICE... |
commit | commitdiff | tree |
2020-07-23 |
Jean THOMAS | vendor.lattice_ecp5: add missing differential IO types. |
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2020-07-22 |
whitequark | back.rtlil: lower maximum accepted wire size. |
commit | commitdiff | tree |
2020-07-22 |
whitequark | sim._pycoro: avoid spurious wakeups. |
commit | commitdiff | tree |
2020-07-22 |
whitequark | CI: replace Travis with GitHub Actions. |
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2020-07-21 |
whitequark | compat.fhdl.bitcontainer: fix value_bits_sign(). |
commit | commitdiff | tree |
2020-07-16 |
whitequark | CI: use WASM yosys instead of building our own. |
commit | commitdiff | tree |
2020-07-15 |
whitequark | back.rtlil: fix guard for division by zero. |
commit | commitdiff | tree |
2020-07-14 |
Filipe Laíns | docs: add install instructions for arch |
commit | commitdiff | tree |
2020-07-14 |
whitequark | CI: run on pull requests as well, not just pushes. |
commit | commitdiff | tree |
2020-07-13 |
whitequark | lib.cdc: fix typo. |
commit | commitdiff | tree |
2020-07-13 |
Jacob Lifshay | sim.pysim: write the next, not curr signal value to... |
commit | commitdiff | tree |
2020-07-11 |
whitequark | sim.pysim: use VCD aliases to reduce space and time... |
commit | commitdiff | tree |
2020-07-08 |
whitequark | sim: simplify. NFC. |
commit | commitdiff | tree |
2020-07-08 |
whitequark | back.pysim→sim.pysim; split into more manageable parts. |
commit | commitdiff | tree |
2020-07-08 |
whitequark | vendor.xilinx_{7series,ultrascale}: remove `grade`... |
commit | commitdiff | tree |
2020-07-08 |
whitequark | back.pysim: only extract signal names if VCD is requested. |
commit | commitdiff | tree |
2020-07-08 |
whitequark | back.pysim: reset timeline as well. |
commit | commitdiff | tree |
2020-07-08 |
whitequark | back.pysim: simplify. NFC. |
commit | commitdiff | tree |
2020-07-08 |
whitequark | back.pysim: extract timeline handling to class _Timelin... |
commit | commitdiff | tree |
2020-07-08 |
whitequark | back.pysim: extract simulator commands to sim._cmds... |
commit | commitdiff | tree |
2020-07-08 |
whitequark | back.pysim: simplify. NFC. |
commit | commitdiff | tree |
2020-07-07 |
awygle | hdl.ast: don't inherit Shape from NamedTuple. |
commit | commitdiff | tree |
2020-07-07 |
whitequark | back.pysim: simplify. |
commit | commitdiff | tree |
2020-07-07 |
whitequark | back.pysim: simplify. NFC. |
commit | commitdiff | tree |
2020-07-07 |
whitequark | back.pysim: simplify. NFC. |
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