gem5.git
2020-01-06 Gabe Blackarch,sim: Use the guest ABI mechanism with pseudo instr...
2020-01-06 Adrian Herreraarch-arm: Semihosting, specify files root dir
2020-01-06 Michiel van Toldev-arm: Fix SMMUv3 walkMasks in page table ops
2020-01-06 Giacomo Travaglinidev-arm: Fix SMMUv3 16KB next-level table address masking
2020-01-06 Adrian Herreradev-arm: GICv3, handle GICR_ICFGR0 WI behaviour
2020-01-06 Nikos Nikolerismem-cache: Avoid write merging if there are reads in...
2020-01-06 Adrian Herreraconfigs-arm: enable PMU instantiation in CpuCluster
2020-01-03 Yu-hsin Wangsim: Move destructor of Port to public
2020-01-03 Giacomo Gabriellicpu: Fix issue with MinorCPU predicated-false mem....
2020-01-03 Gabor Dozsacpu: Disable MinorCPU value forwarding with write strobes
2020-01-03 Bobby R. Brucemisc: Added 'fastmodel' to MAINTAINERS
2019-12-30 Chun-Chen TK Hsufastmodel: Fix compilation errors
2019-12-27 Gabe Blackfastmodel: Move ARM but not CortexA76 specific bits...
2019-12-27 Gabe Blackfastmodel: Move the ARM IRIS threadcontext into CortexA76.
2019-12-27 Gabe Blackfastmodel: Mostly collapse ARM base classes for the...
2019-12-27 Gabe Blackfastmodel: Checkpoint the TCs when checkpointing a...
2019-12-27 Gabe Blackfastmodel: Handle "special" vector regs without calling...
2019-12-24 Gabe Blackfastmodel: Implement readVecRegFlat for ArmThreadContext.
2019-12-24 Gabe Blackfastmodel: Determine what space to use for breakpoints...
2019-12-23 Gabe Blackfastmodel: Implement PC based events.
2019-12-23 Giacomo Travaglinitests: Always print stderr in gem5 Fixtures
2019-12-21 Daniel R. Carvalhobase: Fix negative op-assign of SatCounter
2019-12-20 Giacomo Travagliniconfigs: arm realview(64) regressions using VExpress_GE...
2019-12-20 Jui-min Leesystemc: Fix tlm2 socket integration
2019-12-20 Jui-min Leearch-arm: Fix clang warnings
2019-12-19 AdriĆ  Armejacharch-arm: Fix decoding of LDFF1x scalar plus scalar
2019-12-18 Adrian Herreraarch-arm: Semihosting, fix SYS_FLEN
2019-12-18 Adrian Herrerasim: kernelExtras optional load addresses
2019-12-18 Adrian Herrerapython: fix "fatal" usage in fdthelper
2019-12-18 Adrian Herreraarch-arm: Secure EL2 checking
2019-12-18 Adrian Herreraarch-arm: AArch64 trap check, arbitrary ECs/Imms
2019-12-18 Gabe Blackx86: Fix some bugs with KVM in SE mode on Intel machines.
2019-12-17 Gabe Blacksim: Include some required headers in the syscall debug...
2019-12-17 Gabe Blackfastmodel: Tell fast model not to shutdown when time...
2019-12-17 Gabe Blackfastmodel: Implement port proxies.
2019-12-17 Gabe Blackfastmodel: Create a TLB model which uses IRIS to do...
2019-12-17 Gabe Blackfastmodel: Add an address translation mechanism to...
2019-12-17 Jason Lowe... misc: Add Giacomo Travaglini to PMC
2019-12-17 Nikos Nikolerisbase: Fix AddrRange::isSubset() check
2019-12-17 Bobby R. Brucetests: Setup Kokoro to run the GTest suite.
2019-12-17 Bobby R. Brucescons: Added channel_addr.cc dependency to channel_addr...
2019-12-17 Gabe Blackfastmodel: Add a header for IRIS MSN constants.
2019-12-17 Gabe Blackconfig: Default the indirect branch predictor to "None".
2019-12-16 Adrian Herrerasim: kernelExtras if no kernel provided
2019-12-13 Ciro Santillidev-virtio,configs: expose 9p diod virtio on ARM
2019-12-13 Ciro Santillidev-virtio: VIO9P turns on diod verbose output with...
2019-12-13 Ciro Santillidev-virtio: don't set the 9p default root
2019-12-13 Ciro Santillidev-virtio: use diod basename as the default 9p path
2019-12-12 Daniel R. Carvalhomem: Encapsulate mapping gem5 to host address space
2019-12-12 Daniel R. Carvalhomem-cache: Move unused prefetches counter update
2019-12-12 Gabe Blackpython: Convert terminal escape sequences to strings.
2019-12-11 Giacomo Travagliniarch-arm: Always initialize SVE memData
2019-12-11 Giacomo Travagliniarch-arm: Avoid creating an empty byteEnable vector
2019-12-11 Giacomo Travaglinicpu: Replace empty byteEnable check with Request::isMasked
2019-12-11 Giacomo Travaglinicpu: Fix coding style (byteEnable->byte_enable)
2019-12-11 Giacomo Travaglinicpu: Add byteEnable assertions to readMem and initateMe...
2019-12-10 Gabe Blacksim,arch: Collapse the ISA specific versions of m5Syscall.
2019-12-10 Gabe Blackarch,cpu,sim: Push syscall number determination up...
2019-12-10 Gabe Blackx86: Stop manually clearing RFLAGS.RF after a system...
2019-12-10 Gabe Blackarch: Get rid of the now unused setSyscallArg.
2019-12-10 Gabe Blackarch: Stop using setSyscallArg to set argc and argv.
2019-12-10 Gabe Blacksim: Add a wrapper/subclass for SyscallDesc which uses...
2019-12-10 Gabe Blacksim: Add a mechanism to translate ABIs to call host...
2019-12-10 Gabe Blacksim: Get rid of the now unused SyscallDesc flags and...
2019-12-10 Gabe Blackarch: Use ignoreWarnOnceFunc instead of the WarnOnce...
2019-12-10 Gabe Blacksim: Reintroduce the ignoreWarnOnceFunc syscall handler.
2019-12-10 Gabe Blacksim: Make the syscalls use the SyscallReturn suppressio...
2019-12-10 Adrian Herreradev-arm: GenericTimer, configurable base and low freqs
2019-12-10 Adrian Herreradev-arm: GenericTimer, freq as 32-bit value
2019-12-10 Giacomo Travagliniarch-arm: Disambuiguate NumFloatV7ArchRegs usage
2019-12-10 Giacomo Travagliniarch-arm: Unify VLdmStm behaviour when reg out of index
2019-12-10 Giacomo Travagliniarch-arm: Fix NumVecV7ArchRegs value (64->16)
2019-12-10 Giacomo Travagliniarch-arm: Reorder arch/arm/registers.hh constants
2019-12-10 Giacomo Travagliniarch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
2019-12-09 Giacomo Travaglinitests: AArch64 Linux as quick regressions (instead...
2019-12-09 Giacomo Travaglinimem: Add Request::isMasked to check for byte strobing
2019-12-09 Giacomo Travaglinimem: Add byteEnable copy to Request copy constructor
2019-12-09 Rahul Thakurtests: Increase jenkins test timeout to 4 hours.
2019-12-08 Alec Roelkearch-riscv: set MaxMiscDestRegs to 2
2019-12-07 Gabe Blackscons: Set the partial linking group for EXTRAS dirs.
2019-12-07 Gabe Blackscons: Fixes to improve python 3 support.
2019-12-06 Daniel R. Carvalhoutil: Add a git commit-msg hook
2019-12-06 Gabe Blackkvm,arm: Update the KVM ARM v8 CPU to use vector regs.
2019-12-06 Xin Ouyangarch-riscv: fix asmtest concurrent issues.
2019-12-05 Andrea Mondelliarch-x86: missing override specifier
2019-12-05 marjanfariborzarch-x86: Adding LDDQU instruction
2019-12-04 Gabe Blacksim: Add a suppression mechanism to the SyscallReturn...
2019-12-04 Gabe Blacksim: Small style fixes in sim/syscall_return.hh.
2019-12-04 Gabe Blacksim: Change the syscall executor to a std::function.
2019-12-04 Gabe Blacksparc: Fix the getresuidFunc prototype.
2019-12-04 Gabe Blacksparc: Fix the predecoder's moreBytes method.
2019-12-03 Gabe Blacksystemc: Purposefully *expose* bind in the initiator...
2019-12-03 Gabe Blackfastmodel: Switch the diagnostic pragmas to GCC from...
2019-12-03 Bobby R. Brucemisc: CONTRIBUTING.md to advise linking Jira Issues...
2019-12-03 Brandon Pottercpu,sim-se: move error checks in syscall methods
2019-12-03 Gabe Blacksystemc,fastmodel: Use the gem5_scons error and warning...
2019-12-03 Gabe Blacksystemc: Suppress a spurious clang warning in the syste...
2019-12-03 Gabe Blacksystemc: Fix up some lingering Accellera specific code...
2019-12-03 Ciro Santillibase: add the FmtStackTrace debug option
2019-12-03 Giacomo Travaglinisim-se: Avoid function overloading for syscall implemen...
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