2022-03-24 |
Luke Kenneth... | increase delay on ECP5 ulx3s |
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2022-03-24 |
Luke Kenneth... | check ulx3s, add CRG support for ulx3s |
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2022-03-24 |
Luke Kenneth... | establish power-on reset stabilisation for Arty A7... |
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2022-03-22 |
Luke Kenneth... | add hack to modify VERSA_ECP5 85F platform to speed... |
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2022-03-22 |
Luke Kenneth... | adding hyperram for arty a7 and also adding a workaroun... |
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2022-03-20 |
Luke Kenneth... | add microwatt hello_world source |
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2022-03-20 |
Luke Kenneth... | crank A7 FPGA speed down to experiment |
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2022-03-20 |
Luke Kenneth... | code-comments |
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2022-03-20 |
Luke Kenneth... | fix Arty A7-100t PLL with quick demo |
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2022-03-20 |
Luke Kenneth... | first cut at Arty A7 Clock-Reset-Generator with S7 PLL |
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2022-03-20 |
Luke Kenneth... | beginnings of arty a7 clock-reset-generator |
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2022-03-19 |
Luke Kenneth... | add VERSA_ECP5 85F custom board |
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2022-03-19 |
Luke Kenneth... | move quick read/write test for hyperram in coldboot.c |
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2022-03-19 |
Luke Kenneth... | set IO_TYPE 3.3v attribute on HyperRAM not IOSTANDARD |
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2022-03-19 |
Luke Kenneth... | correct pin names for HyperRAMResource, indent spi0... |
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2022-03-19 |
Luke Kenneth... | fixed hyperram pin names which was stopping verilator... |
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2022-03-19 |
Luke Kenneth... | disable hyperram for now (under investigation) |
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2022-03-19 |
Luke Kenneth... | adding in hyperram peripheral |
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2022-03-18 |
Luke Kenneth... | whitespace / module-import / comments / tidyup |
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2022-03-18 |
Luke Kenneth... | beginning to add hyperram module |
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2022-03-18 |
Luke Kenneth... | whitespace cleanup and make SPI core (temporarily)... |
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2022-03-17 |
Luke Kenneth... | work-in-progress on DDR3 firmware. sigh |
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2022-03-17 |
Luke Kenneth... | comment about icarus verilog to speed up simulations |
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2022-03-16 |
Raptor Engineering... | Add initial Tercel SPI controller |
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2022-03-10 |
Luke Kenneth... | sigh gramWishbone is not WB4-pipeline-burst-compliant |
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2022-03-09 |
Luke Kenneth... | fix WB6to32 downconverter with stall signalling |
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2022-03-09 |
Luke Kenneth... | add stall signal to arbiter, assume nmigen-soc takes |
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2022-03-04 |
Luke Kenneth... | add experimental stall-capable 64-to-32 wishbone converter |
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2022-03-02 |
Luke Kenneth... | lots of comments in the yosys script file |
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2022-03-02 |
Luke Kenneth... | invert reset and chip-select on dram, and initialise... |
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2022-03-02 |
Luke Kenneth... | forgot to include firmware in build for new icarus... |
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2022-03-01 |
Luke Kenneth... | add new icarus-versa-ecp5 platform in ls2.py |
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2022-02-28 |
Luke Kenneth... | increase timescale of icarus simulation |
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2022-02-28 |
Luke Kenneth... | fix undefined uart_tx in icarus simulation, icarus... |
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2022-02-28 |
Luke Kenneth... | use a slightly different yosys initialisation sequence... |
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2022-02-28 |
Luke Kenneth... | fix memory issue in yosys synth for icarus |
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2022-02-28 |
Luke Kenneth... | add icarus simulation of ls2 with DDR3 and ECP5 models |
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2022-02-23 |
Luke Kenneth... | invert CRG reset on PLL see if it makes any difference |
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2022-02-23 |
Luke Kenneth... | add comments about DRAM sync clock being identical... |
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2022-02-22 |
Luke Kenneth... | xdr=4 missing on ddr3 platform request for VERSA_ECP5 |
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2022-02-21 |
Luke Kenneth... | lengthen cdelay pauses by a factor of 10 |
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2022-02-21 |
Luke Kenneth... | * use readl and writel for accessing memory |
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2022-02-21 |
Luke Kenneth... | use microwatt mmu powerpc.lds with better stack space |
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2022-02-20 |
Luke Kenneth... | fix dfi initialisation and calibration to use |
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2022-02-20 |
Luke Kenneth... | set RAM base to #defined DRAM_BASE not hard-coded value |
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2022-02-20 |
Luke Kenneth... | for simulatio keep the simulated dram in the |
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2022-02-20 |
Luke Kenneth... | add fake (sim) DRAM from gram library |
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2022-02-19 |
Luke Kenneth... | match up dram initialisation parameters |
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2022-02-19 |
Luke Kenneth... | put together coldboot startup firmware |
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2022-02-19 |
Luke Kenneth... | hm -abc9 seems to be working, and without -nowidelut |
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2022-02-18 |
Luke Kenneth... | add DRAM class to DDR3Soc |
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2022-02-18 |
Luke Kenneth... | add FPGA argument to DDR3SoC |
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2022-02-18 |
Luke Kenneth... | add microwatt console lib and #includes |
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2022-02-18 |
Luke Kenneth... | make cpu optional (test purposes), make bios optional, |
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2022-02-16 |
Luke Kenneth... | remove minerva cpu |
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2022-02-16 |
Luke Kenneth... | drop clock frequency to 25 mhz and disable abc9 (it... |
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2022-02-16 |
Luke Kenneth... | add openocd load command for ecp5 |
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2022-02-16 |
Luke Kenneth... | wildcards never ok. update comments |
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2022-02-16 |
Luke Kenneth... | add copyright notices |
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2022-02-16 |
Luke Kenneth... | update ECP5 PLL to accept parameters for setting arbitr... |
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2022-02-16 |
Luke Kenneth... | add start of README as reminder |
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2022-02-16 |
Luke Kenneth... | * add uart_pins to UART16550 peripheral so they get... |
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2022-02-16 |
Luke Kenneth... | * disable DDR3 for now |
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2022-02-15 |
Luke Kenneth... | connect up stall signals (fake) for WB Classic compliance |
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2022-02-15 |
Luke Kenneth... | alternative uart wishbone mapping which just takes... |
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2022-02-15 |
Luke Kenneth... | attempt to do 8-bit downconvert on wishbone bus for... |
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2022-02-15 |
Luke Kenneth... | correct syscon bus address to 0xC000_0000 |
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2022-02-15 |
Luke Kenneth... | add microwatt SYSCON peripheral at 0xc000_0000 |
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2022-02-15 |
Luke Kenneth... | increase size of bootmem |
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2022-02-15 |
Luke Kenneth... | add interrupt controller module, remove stall feature... |
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2022-02-15 |
Luke Kenneth... | FLGA_TARGET=verilator not uppercase |
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2022-02-14 |
Luke Kenneth... | add external cpu |
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2022-02-14 |
Luke Kenneth... | convert boot rom to bootmem and get first hello_world... |
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2022-02-14 |
Luke Kenneth... | add IBM microwatt CC4 license and copyright notices |
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2022-02-14 |
Luke Kenneth... | add first cut of verilator simulation, over from microwatt |
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2022-02-14 |
Luke Kenneth... | add verilog build option, make DDR3 PHY optional, add... |
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2022-02-13 |
Luke Kenneth... | add future sim option (needs Simulated DDR PHY) |
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2022-02-13 |
Luke Kenneth... | add build to gitignore |
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2022-02-13 |
Luke Kenneth... | rename examples to src |
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2022-02-13 |
Luke Kenneth... | not for any good reason, separate adding the uart16550... |
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2022-02-13 |
Luke Kenneth... | add MemoryMap to UART16550 (TODO, put that into UART165... |
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2022-02-13 |
Luke Kenneth... | start adding uart16550 |
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2022-02-13 |
Luke Kenneth... | select a firmware file |
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2022-02-13 |
Luke Kenneth... | allow selection of alternative FPGAs at commandline |
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2022-02-13 |
Luke Kenneth... | add blinky lights so we know FPGA is alive |
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2022-02-13 |
Luke Kenneth... | make firmware and cpu optional for now to get a basic... |
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2022-02-12 |
Luke Kenneth... | begin a tidyup on the example |
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2022-02-10 |
Luke Kenneth... | resolve imports, whitespace, add Copyright |
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2022-02-10 |
Luke Kenneth... | add crg.py |
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2022-02-10 |
Luke Kenneth... | update contributors |
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2022-02-10 |
Luke Kenneth... | sort out license and headers for NLnet and NGI POINTER... |
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2022-02-10 |
Luke Kenneth... | add gram soc example and license and contributors |
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2022-02-09 |
Luke Kenneth... | empty first commit |
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