openpower-isa.git
2022-07-28 Dmitry Selyutinsv_binutils: include SVP64 context header
2022-07-28 Dmitry Selyutinsv_binutils: remove separate CRs table
2022-07-28 Jacob LifshayDOUBLE2SINGLE: convert doc comments to docstring
2022-07-28 Jacob Lifshayre-convert frsp pseudocode
2022-07-28 Jacob Lifshaytry to add some line numbers to ast -- helps with debugging
2022-07-28 Jacob Lifshayswitch ast for assignment to tuple to use the python...
2022-07-28 Jacob Lifshayfix line number tracking
2022-07-28 Jacob Lifshayadd handy re-indenting script
2022-07-27 Jacob Lifshaygitlab-ci.yml: stop testing after 5 failures
2022-07-27 Jacob Lifshayshrink build log
2022-07-27 Jacob Lifshayadd another test and fix broken fishmv pseudocode
2022-07-27 Luke Kenneth... add extra fmvis to see what is going on
2022-07-27 Konstantinos... Fix fmvis & fishmv bit handling for d0, add tests for...
2022-07-27 Konstantinos... Add fishmv instruction (bug #887)
2022-07-27 Konstantinos... fix wrong shift in fmvis, use correct immediates in...
2022-07-26 Luke Kenneth... update comments in fmvis case
2022-07-26 Luke Kenneth... add first FP "expected state" use it in fmvis
2022-07-26 Luke Kenneth... bit more docs on fmvis
2022-07-26 Luke Kenneth... off-by-one in declaration of pattern-match XO for fmvis
2022-07-26 Luke Kenneth... add some more example fmvis to work out which is LSB...
2022-07-26 Luke Kenneth... add example fmvis instruction to trans/svp64.py
2022-07-26 Luke Kenneth... dang.
2022-07-26 Luke Kenneth... Revert "set IN1 to NONE for fmvis", in1 is FRS.
2022-07-26 Luke Kenneth... use DOUBLE helper function in fmvis
2022-07-26 Luke Kenneth... annoying. DX-Form is one exception to the rule of havin...
2022-07-26 Konstantinos... set IN1 to NONE for fmvis
2022-07-26 Konstantinos... fix form and pseudo-code for fmvis, tests in 64-bit...
2022-07-26 Luke Kenneth... whitespace cleanup
2022-07-26 Konstantinos... fix fmvis decoder, it's now a 2-operand instruction
2022-07-26 Konstantinos... Add fmvis instruction + tests, bug #887
2022-07-25 Dmitry Selyutinsvp64.py: fix alignment
2022-07-25 Dmitry Selyutinsvp64.py: update svindex operands
2022-07-23 Luke Kenneth... dump output from pypowersim_fp
2022-07-21 Luke Kenneth... whoops missing variables in new subfunction after
2022-07-21 Luke Kenneth... add dsubstep to ISACaller
2022-07-21 Luke Kenneth... sort out subvl unit test with expected results
2022-07-21 Luke Kenneth... fix loopend conditions for subvectors in ISACaller
2022-07-20 Luke Kenneth... rename substep to ssubstep, add dsubstep to SVP64State
2022-07-20 Luke Kenneth... add first subvl unit test, subvl comes from
2022-07-18 Luke Kenneth... move D-Immediate rewriting in ISACaller into separate...
2022-07-18 Luke Kenneth... move inputs in ISACaller into get_input()
2022-07-18 Luke Kenneth... move debug remap to ISACaller.remap_debug()
2022-07-18 Luke Kenneth... whitespace and function-return code-morphing in ISACaller
2022-07-18 Luke Kenneth... move another function in ISACaller (check_write)
2022-07-18 Luke Kenneth... begin function split in ISACaller
2022-07-18 Luke Kenneth... remove duplicate code create ISACaller.advance_svstate_...
2022-07-18 Luke Kenneth... add SUBVL (substep) support to PowerDecoder2 and to...
2022-07-18 Luke Kenneth... add substep getter/setter to SVP64State
2022-07-18 Luke Kenneth... rename SVSTATE.svstep to SVSTATE.substep to avoid
2022-07-16 Luke Kenneth... simplify remapyield.py, skip shows the bit to be skipped
2022-07-14 Luke Kenneth... got fed up of long list of ifs for manually decoded...
2022-07-14 Jacob Lifshayadd jit_test for testing icbi and isync
2022-07-12 Luke Kenneth... add DX-Form FRS for fmvis
2022-07-12 Luke Kenneth... add recognition of 0xNNN and 0bMMMM to sv/trans/svp64.py
2022-07-12 Luke Kenneth... add FRS as destination to PowerDecoder2 DecodeOut
2022-07-11 Luke Kenneth... add mm=1 svindex test, setting single targetted SVSHAPE
2022-07-11 Luke Kenneth... fix issue in SelectableInt.__rsub__ causing truncation...
2022-07-11 Luke Kenneth... fix issue in SelectableInt using slices involving Selec...
2022-07-11 Andrey MiroshnikovAdded insn initialisation for grev() func
2022-07-11 Andrey MiroshnikovMissed another two form sub-headings
2022-07-11 Andrey MiroshnikovMissed another two form sub-headings
2022-07-11 Andrey MiroshnikovFixed missing space for form headings
2022-07-11 Luke Kenneth... compute 2nd svindex dimension using unsignee compare
2022-07-10 Luke Kenneth... add yx svindex test, needed to compute size of 2nd dim
2022-07-10 Luke Kenneth... Indexed SVSHAPE add bypass mode when dim sizes are 1
2022-07-10 Luke Kenneth... add second svindex test, modulo 3
2022-07-10 Luke Kenneth... fix svindex pseudocode, set large 2nd dim on nonskip
2022-07-10 Luke Kenneth... fix svindex unit test, experiment setting dimensions
2022-07-10 Luke Kenneth... fix SVSHAPE iterator for index case, stop deepcopy
2022-07-10 Luke Kenneth... add new svindex sv.add test with arbitrary index map
2022-07-10 Luke Kenneth... non-persistence enabled on svindex as well as svremap
2022-07-10 Luke Kenneth... fix svindex pseudocode
2022-07-09 Luke Kenneth... pass GPR to SVSHAPEs in ISACaller
2022-07-09 Luke Kenneth... add gpr lookup in Indexed SVSHAPE iterator (no elwidths...
2022-07-09 Luke Kenneth... rough unit test ahowing Index REMAP basically functiona...
2022-07-09 Luke Kenneth... add support for Indexed mode in SVSHAPE
2022-07-09 Luke Kenneth... add storing of shape in requested SVSHAPE in svindex...
2022-07-06 Luke Kenneth... move DX Form
2022-07-06 Luke Kenneth... add first stub of svindex pseudocode
2022-07-06 Dmitry Selyutinaudio/mp3: convert asm to the new notation
2022-07-06 Dmitry Selyutinsvp64.py: allow macros as register names
2022-07-06 Dmitry Selyutinsvp64.py: generate registers
2022-07-06 Luke Kenneth... add svindex to power_enums.py, minor_22.csv
2022-07-06 Luke Kenneth... indentation on fields.txt to make it more markdown...
2022-07-06 Luke Kenneth... convert Logical svp64_cases.py to new vector reg form
2022-07-06 Luke Kenneth... convert ALU svp64_cases.py to new vector reg form
2022-07-06 Luke Kenneth... converted test_caller_svstate.py to new reg format
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64.py to new vector numbering...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_predication.py to new vector...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_ldst.py to new vector numberi...
2022-07-05 Andrey MiroshnikovUpdated the nmigen.sim import
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_fft.py to new vector numberin...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_bc.py to new vector numbering...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_dct.py to new vector numberin...
2022-07-05 Luke Kenneth... converted test_caller_svp64_matrix.py to new reg format
2022-07-05 Luke Kenneth... converted test_caller_svp64_fp.py to new reg format
2022-07-05 Luke Kenneth... converted test_caller_svp64_mapreduce.py to new reg...
2022-07-05 Luke Kenneth... convert test_caller_setvl.py to new vector numbering...
2022-07-05 Luke Kenneth... add "*%" and "*" vector-numbering convention
2022-07-05 Luke Kenneth... add note about bug #884 new reg vector naming convention
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