| 2018-09-30 |
Luke Kenneth... | yuk. break id_regs.py being a generic tool by skipping... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | fix bug in sv template where FRS2 was checking rs3 |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add checks for RVC registers to sv template |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add sv_insn_t overloads for rvc registers |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | also arrange for id_regs.py to identify compressed... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | a LOT of debugging and fixing, sv loop actually working |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | move SV CSRs to user-read-write |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add near-duplicate of SV CFG REG CSRs, for predication |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add implementation of CSR SV CFG regs 0-7 |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | assign SV REG CSRs (using new union ability) |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | make sv csr tables a union so they can be assigned... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add support for CSR_SVVL to CSRRWI as well |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | fix bug in CSR set SVVL: val has already been looked up |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add stub for SV REG configs |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | stop a compiler warning |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | reorganise from moving sv_pred_* and sv_reg_* tables... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | have to move SV CSRs into processor_t |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add 8 CSRs for registers and predication each |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | whoops dont need separate SVSETVL/SVGETVL CSRs |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | revert addition of svsetvl as an actual opcode, add... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | Revert "sv setvl as a csr not going to work, add getvl... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | Revert "manually add svsetvl instruction" |
commit | commitdiff | tree |
| 2018-09-28 |
Luke Kenneth... | manually add svsetvl instruction |
commit | commitdiff | tree |
| 2018-09-28 |
Luke Kenneth... | sv setvl as a csr not going to work, add getvl only |
commit | commitdiff | tree |
| 2018-09-27 |
Luke Kenneth... | adding sv vector length CSR to processor state, and... |
commit | commitdiff | tree |
| 2018-09-27 |
Luke Kenneth... | add sv predication function |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | save some cpu cycles by |ing the checks for vectorop... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | whoops vectorop has to be |= not &= to accumulate ... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | cache the sv redirected register values on each loop |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | remembered that the use of sv registers have to be... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | clarify comments on (key strategic) sv_insn_t::remap... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | actually implement sv register re-mapping |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | ok this is tricky: an extra parameter has to be passed... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | move sv remap function to sv.cc (not inline) |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | check if register redirection is active, and if vectori... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | comment why sv_insn_t is set up the way it is; add... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | easier to #define USING_NOREGS if the opcode does not... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | include auto-generated identification of use of registe... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | shuffle things around a bit for sv, put rv32/64_name... |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | skip id_reg.py parsing its own output; stop outputting... |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | change to instruction template parsing, create one... |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | add decode.h header to sv.h |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | rename sv vlen to sv voffs, add csr and reg tables |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | add reference to vector length in sv |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | use sv_insn_t class in instruction template |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | add sv_insn_t class (inherits from insn_t) |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | argh cant virtualise rd/rs1-3, due to union usage with... |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | sv: rd, rs1/2/3 become virtual so that sv_insn_t can... |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | clarify sv cam table |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | define CSR and register tables for SV |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | remove unneeded use of AM_CONDITIONAL |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | add #define for SPIKE_SIMPLEV, re-run autoreconf |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | create #defines from identified registers, per opcode |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | clarify docstring on id_regs.py |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | add function identifying the registers in each emulated... |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | identify instructions, plan: extract registers |
commit | commitdiff | tree |
| 2018-09-13 |
Andrew Waterman | Update README master |
commit | commitdiff | tree |
| 2018-09-06 |
Tim Newsome | Merge pull request #235 from riscv/sba |
commit | commitdiff | tree |
| 2018-09-05 |
Tim Newsome | Fix cut-and-paste bug in 64-bit SBA loads. |
commit | commitdiff | tree |
| 2018-08-24 |
Andrew Waterman | Handle spike-dasm inputs with leading 0x correctly |
commit | commitdiff | tree |
| 2018-08-24 |
Tim Newsome | Add dummy custom debug registers, to test OpenOCD.... |
commit | commitdiff | tree |
| 2018-08-24 |
Andrew Waterman | Fix several disassembler bugs |
commit | commitdiff | tree |
| 2018-08-23 |
Andrew Waterman | Add --disable-dtb option to suppress writing the DTB... |
commit | commitdiff | tree |
| 2018-08-22 |
Andrew Waterman | Make IRQ_COP read-only/undelegable unless coprocessor... |
commit | commitdiff | tree |
| 2018-08-21 |
Andrew Waterman | Instantiate disassembler after max_xlen is known |
commit | commitdiff | tree |
| 2018-08-18 |
Andrew Waterman | Don't increment instret immediately after it is written... |
commit | commitdiff | tree |
| 2018-08-10 |
Tim Newsome | Fix 2 trigger corner cases. (#229) |
commit | commitdiff | tree |
| 2018-07-31 |
Andrew Waterman | Make sstatus.MXR readable |
commit | commitdiff | tree |
| 2018-07-23 |
SeungRyeol Lee | Fix using the uninitialized disassemble object. (#220) |
commit | commitdiff | tree |
| 2018-07-10 |
Andrew Waterman | Refactor and fix LR/SC implementation (#217) |
commit | commitdiff | tree |
| 2018-06-12 |
Tim Newsome | Merge pull request #212 from riscv/hartsel |
commit | commitdiff | tree |
| 2018-06-11 |
Tim Newsome | Update debug_defines.h |
commit | commitdiff | tree |
| 2018-05-31 |
Andy Wright | Put simif_t declaration in its own file. (#209) |
commit | commitdiff | tree |
| 2018-05-18 |
Prashanth Mundkur | Fix install of missed header. (#207) |
commit | commitdiff | tree |
| 2018-05-18 |
Prashanth Mundkur | Extract out device-tree generation and compilation... |
commit | commitdiff | tree |
| 2018-05-04 |
Andrew Waterman | Revert "C.LWSP and C.LDSP with rd=0 are legal instructions" |
commit | commitdiff | tree |
| 2018-05-04 |
Andrew Waterman | C.LWSP and C.LDSP with rd=0 are legal instructions |
commit | commitdiff | tree |
| 2018-05-01 |
Andrew Waterman | Fix commit log for serializing instructions |
commit | commitdiff | tree |
| 2018-04-30 |
Andrew Waterman | Only break out of the simulator loop on WFI, not on... |
commit | commitdiff | tree |
| 2018-04-29 |
Andrew Waterman | When no arguments are passed, print spike help, not... |
commit | commitdiff | tree |
| 2018-04-05 |
Prashanth Mundkur | Allow querying the mmu configuration chosen during... |
commit | commitdiff | tree |
| 2018-04-04 |
Andrew Waterman | Revert "Fix for issue #183: No illegal instruction... |
commit | commitdiff | tree |
| 2018-03-30 |
Palmer Dabbelt | Merge pull request #189 from pmundkur/pm-csr-name-api |
commit | commitdiff | tree |
| 2018-03-26 |
Prashanth Mundkur | Add an api to get the name for a CSR. |
commit | commitdiff | tree |
| 2018-03-22 |
Andrew Waterman | Implement Hauser misa.C misalignment proposal (#187) |
commit | commitdiff | tree |
| 2018-03-21 |
Prashanth Mundkur | Fix the access exception during page-table walks to... |
commit | commitdiff | tree |
| 2018-03-19 |
Tim Newsome | Fix spike-dasm. (#184) |
commit | commitdiff | tree |
| 2018-03-19 |
Tim Newsome | Merge pull request #182 from riscv/reset_bits |
commit | commitdiff | tree |
| 2018-03-16 |
Tim Newsome | Implement debug havereset bits |
commit | commitdiff | tree |
| 2018-03-16 |
Andrew Waterman | Merge branch 'deepsrc-b_fix_issue183' |
commit | commitdiff | tree |
| 2018-03-16 |
Shubhodeep... | Fix for issue #183: No illegal instruction exception... |
commit | commitdiff | tree |
| 2018-03-14 |
Prashanth Mundkur | Fix a bug caused by moving misa into state_t. (#180) |
commit | commitdiff | tree |
| 2018-03-13 |
Prashanth Mundkur | Move processor.isa to state.misa, since it really belon... |
commit | commitdiff | tree |
| 2018-03-10 |
Tim Newsome | Fix single stepping csrrw instructions (#178) |
commit | commitdiff | tree |
| 2018-03-08 |
Tim Newsome | Merge pull request #177 from riscv/debug_auth |
commit | commitdiff | tree |
| 2018-03-06 |
Prashanth Mundkur | Narrow the interface used by the processors and memory... |
commit | commitdiff | tree |
| 2018-03-06 |
Prashanth Mundkur | Fix install of a missed header from debug_rom. |
commit | commitdiff | tree |
| 2018-03-06 |
Prashanth Mundkur | Fix a missed header file in the softfloat include install. |
commit | commitdiff | tree |
| 2018-03-03 |
Andrew Waterman | Implement clearing-misa.C-while-PC-is-misaligned proposal |
commit | commitdiff | tree |
| 2018-03-03 |
Andrew Waterman | Enforce 2-byte alignment of mepc/sepc/dpc |
commit | commitdiff | tree |
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