gem5.git
2013-09-30 Andreas Sandbergext: Include libfputils
2013-09-30 Andreas Sandbergx86: Add limited support for extracting function call...
2013-09-30 Andreas Sandbergkvm: x86: Fix segment registers to make them VMX compatible
2013-09-28 Steve Reinhardttests: update reference outputs
2013-09-25 Andreas Sandbergkvm: Add x86 segment register verification to help...
2013-09-25 Andreas Sandbergkvm: Initial x86 support
2013-09-19 Andreas Sandbergkvm: Correctly handle the return value from handleIpr...
2013-09-19 Andreas Sandbergkvm: Fix a case where the run timers weren't armed...
2013-09-19 Andreas Sandbergx86: Add support routines to convert between x87 tag...
2013-09-18 Andreas Sandbergsim: Fix undefined behavior in the pseudo-inst interface
2013-09-18 Andreas Hanssonmem: Fix scheduling bug in SimpleMemory
2013-09-18 Andreas Hanssonswig: Warn on use of incompatible swig/gcc combinations
2013-09-18 Andreas Hanssonswig: Fix issue with circular import in 2.0.9/2.0.10
2013-09-18 Andreas Sandbergx86: Expose the raw hash map of MSRs
2013-09-18 Andreas Sandbergx86: Add support for checking the raw state of an interrupt
2013-09-18 Andreas Sandbergx86: Expose the interrupt vector in faults
2013-09-18 Joel Hestnessconfigs: Fix ruby_fs.py cache line size
2013-09-15 Nilay Vaishstats: update sparc fs due to recent changes to memory...
2013-09-12 Andreas Hanssonconfig: Add voltage domain to Ruby example scripts
2013-09-11 Joel Hestnessruby: Fix Topology throttle connections
2013-09-11 Joel Hestnesscpu: Dynamically instantiate O3 CPU LSQUnits
2013-09-11 Joel Hestnessconfig: Initialize and check cpt_starttick
2013-09-11 Joel Hestnessruby: Statically allocate stats in SimpleNetwork, Switc...
2013-09-09 Nilay Vaishstats: add operator= for DataWrapVec class
2013-09-06 Nilay Vaishstats: ruby: updates due to recent changes.
2013-09-06 Nilay Vaishruby: network: convert to gem5 style stats
2013-09-06 Nilay Vaishruby: network: correct naming of routers
2013-09-06 Nilay Vaishruby: profiler: removes function resourceUsage()
2013-09-06 Nilay Vaishruby: remove undefined message size type
2013-09-06 Nilay Vaishruby: network: removes reset functionality
2013-09-06 Nilay Vaishruby: network: shorten variable names
2013-09-06 Nilay Vaishstats: adds a Formula operator for division
2013-09-06 Nilay Vaishruby: converts sparse memory stats to gem5 style
2013-09-05 Andreas Hanssonsim: Fix clang warning for unused variable
2013-09-04 Andreas Hanssonutil: Add ini string as tooltip info in dot output
2013-09-04 Andreas Hanssonutil: Add colours to the dot output
2013-09-04 Andreas Hanssonutil: Add class name to dot graph and output to svg
2013-09-04 Andreas Hanssontests: Move ISA-independent tests to the NULL ISA
2013-09-04 Andreas Hanssonarch: Resurrect the NOISA build target and rename it...
2013-09-04 Andreas Hanssoncpu: Move the branch predictor out of the BaseCPU
2013-09-04 Andreas Hanssonarch: Header clean up for NOISA resurrection
2013-09-04 Andreas Hanssonalpha: Move system virtProxy to Alpha only
2013-09-04 Andreas Hanssonscons: Enable build on OSX
2013-08-26 Ali SaidiARM: Fix configuration files for bare-metal binaries.
2013-08-24 Steve Reinhardtstats: update eio stats
2013-08-22 Steve Reinhardtutil/regress: set --no-lto on regressions
2013-08-20 Nilay Vaishstats: update ruby.stats, config.ini files for x86...
2013-08-20 Nilay Vaishruby: add option for number of transitions per cycle
2013-08-20 Andreas Hanssoncpu: Fix timing CPU isDrained comment formatting
2013-08-20 Andreas Hanssonbase: Fix VectorPrint initialisation
2013-08-19 Andreas Hanssonstats: Cumulative stats update
2013-08-19 Lena Olsoncpu: Accurately count idle cycles for simple cpu
2013-08-19 Andreas Hanssonconfig: Command line support for multi-channel memory
2013-08-19 Andreas Hanssonmem: Change AbstractMemory defaults to match the common...
2013-08-19 Sascha Bischoffcpu: Fix TrafficGen trace playback
2013-08-19 Andreas Hanssonmem: Use STL deque in favour of list for DRAM queues
2013-08-19 Andreas Hanssonmem: Perform write merging in the DRAM write queue
2013-08-19 Amin Farmahinimem: Replacing bytesPerCacheLine with DRAM burstLength...
2013-08-19 Andreas Hanssoncpu: Fix timing CPU drain check
2013-08-19 Andreas Hanssonalpha: Check interrupts before quiesce
2013-08-19 Sascha Bischoffstats: Fix issue when printing 2D vectors
2013-08-19 Akash Bagdiapower: Add voltage domains to the clock domains
2013-08-19 Andreas Hanssonconfig: Move the memory instantiation outside FSConfig
2013-08-19 Andreas Hanssonmem: Warn instead of panic for tXAW violation
2013-08-19 Andreas Hanssonmem: Allow disabling of tXAW through a 0 activation...
2013-08-19 Andreas Hanssonmem: Add an internal packet queue in SimpleMemory
2013-08-19 Andreas Hanssoncpu: Fix a bug in the O3 CPU introduced by the cache...
2013-08-14 Anthony Gutierrezarm: use -march when compiling m5op_arm.S
2013-08-07 Nilay Vaishruby: slicc: remove double trigger, continueProcessing
2013-08-07 Nilay Vaishruby: slicc: move some code to AbstractController
2013-08-07 Nilay Vaishx86: add tlb checkpointing
2013-07-19 Andreas Sandbergcpu: Remove unused getBranchPred() method from BaseCPU
2013-07-18 Joel HestnessConfigs: Fix up maxtick and maxtime
2013-07-18 Andreas Hanssonconfig: Update script to set cache line size on system
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level
2013-07-18 Xiangyu Dongmem: Add cache class destructor to avoid memory leaks
2013-07-18 Andreas Hanssonscons: Use python-config instead of distutils
2013-07-18 Andreas Hanssonsim: Make MaxTick in Python match the one in C++
2013-07-15 Deyuan Guoloader: Load weak symbols for function tracing
2013-07-15 Umesh Bhaskardebug : Fixes the issue wherein Debug symbols were...
2013-07-12 Steve Reinhardtdev: make BasicPioDevice take size in constructor
2013-07-12 Steve Reinhardtdev: consistently end device classes in 'Device'
2013-07-12 Steve Reinhardtdev/arm: get rid of AmbaDev namespace
2013-07-12 Steve Reinhardtdevices: make more classes derive from BasicPioDevice
2013-07-11 Brad Beckmannruby: removed the very old double trigger hack stable_2013_10_14
2013-07-02 Nilay Vaishregressions: update a couple stats.txt
2013-07-02 Nilay Vaishregressions: update a couple of configs
2013-06-29 Nilay Vaishruby: append transition comment only when in opt/debug
2013-06-29 Nilay Vaishconfigs: rearrange the available options in Options.py
2013-06-29 Nilay Vaishruby: network: remove reconfiguration code
2013-06-29 Nilay Vaishruby: check for compatibility between mem size and...
2013-06-27 Andreas Hanssonstats: Update stats for monitor, cache and bus changes
2013-06-27 Prakash Ramrakhyanimem: Reorganize cache tags and make them a SimObject
2013-06-27 Andreas Hanssonmem: Remove the cache builder
2013-06-27 Andreas Hanssonconfig: Remove Clock parameter multiplication
2013-06-27 Akash Bagdiasim: Add the notion of clock domains to all ClockedObjects
2013-06-27 Andreas Hanssonconfig: Add a BaseSESystem builder for re-use in regres...
2013-06-27 Akash Bagdiaconfig: Rename clock option to Ruby clock
2013-06-27 Akash Bagdiaconfig: Add a system clock command-line option
2013-06-27 Akash Bagdiaconfig: Add a CPU clock command-line option
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