soc.git
2020-09-17 Jacob Lifshayreplace sim._state.timeline.now with sim._engine.now
2020-09-17 Luke Kenneth... add versa ecp5 fpga litex build script
2020-09-16 Cole Poiriercomplete first translation pass of dmi_dtm_xilinx.vhdl...
2020-09-16 Luke Kenneth... make a start on LS180 platform
2020-09-16 Cole Poirierinitial commit of JTAGToDMI debug interface translated...
2020-09-16 Cole Poirieradd template file/starting point (copy of litex/boards...
2020-09-15 Luke Kenneth... add back (totally confusing) accidentally-removed code...
2020-09-15 Luke Kenneth... instantiate MMU from AllFunctionUnits
2020-09-15 Luke Kenneth... do not need FAST regs in MMU
2020-09-15 Luke Kenneth... comment mmu test
2020-09-15 Luke Kenneth... add edge-triggering to dcache/mmu "valid"
2020-09-15 Luke Kenneth... add set MTSPR prtbl to mmu unit test
2020-09-15 Luke Kenneth... add OP_MFSPR to mmu
2020-09-15 Luke Kenneth... use convenience vars
2020-09-15 Luke Kenneth... add OP_TLBIE to mmu fsm
2020-09-15 Luke Kenneth... add OP_DCBZ to mmu fsm, needs RA to be added to MMU...
2020-09-15 Luke Kenneth... add MMU MTSPR connection into FSM
2020-09-15 Luke Kenneth... add in MMU and DCache into MMU FSM
2020-09-15 Luke Kenneth... moved PLRU to nmutil
2020-09-15 Luke Kenneth... add mmu fsm
2020-09-15 Luke Kenneth... remove more (confusing/spurious) types, should be in...
2020-09-15 Luke Kenneth... remove more (confusing/spurious) types, should be in...
2020-09-15 Luke Kenneth... remove more (confusing/spurious) types, should be in...
2020-09-15 Luke Kenneth... removed (confusing/spurious) types, should be in .pyi...
2020-09-15 Luke Kenneth... add MMU FunctionUnit
2020-09-15 Luke Kenneth... mmu uses RB, go with it
2020-09-15 Luke Kenneth... add OP_TLBIE
2020-09-15 Luke Kenneth... add mmu initial pipe_data.py
2020-09-15 Luke Kenneth... add extra "modes" to PortInterface
2020-09-15 Luke Kenneth... syntax error correction
2020-09-15 Luke Kenneth... add inline comments into icache.py
2020-09-14 Cole Poiriericache.py add missing funciton bodies, add missing...
2020-09-14 Luke Kenneth... increase TLB_NUM_WAYS to 4
2020-09-14 Luke Kenneth... vhdl conversion not really working for plru
2020-09-14 Luke Kenneth... add array signal names
2020-09-14 Luke Kenneth... rename plru input
2020-09-14 Luke Kenneth... rename plru input
2020-09-14 Luke Kenneth... reorg mmu lookup test so it is called twice
2020-09-14 Luke Kenneth... TLB PLRUs are of TLB_WAY_BITS width
2020-09-14 Luke Kenneth... fix mmu perms/lookup in dcache
2020-09-14 Luke Kenneth... whitespace
2020-09-14 Luke Kenneth... remove duplicated signal
2020-09-14 Luke Kenneth... comments on icache
2020-09-14 Luke Kenneth... get rid of rst
2020-09-14 Luke Kenneth... use word_select
2020-09-14 Luke Kenneth... add mmu-dcache test
2020-09-14 Cole Poiriericache.py connect up all the sub-functions, fix typos...
2020-09-14 Cole Poiriericache.py add parameters to 'process' functions, fix...
2020-09-13 Cole Poiriericache.py move get/read/write functions out of ICache...
2020-09-13 Cole Poiriericache.py copy simulation code from dcache.py, fix...
2020-09-13 Cole Poiriericache.py fix syntax, move all constants and Array...
2020-09-13 Cole Poiriericache.py fix syntax errors that occured when running...
2020-09-13 Luke Kenneth... dcache truncate wishbone address, store real_addr in...
2020-09-13 Luke Kenneth... last mmu get seems ok
2020-09-13 Luke Kenneth... whoops recursion error v.shift calculated from v.shift
2020-09-13 Luke Kenneth... more experimenting with mmu READ_WAIT state
2020-09-13 Luke Kenneth... radix tree wait error, investigating
2020-09-13 Luke Kenneth... mmu test starting to make sense
2020-09-13 Luke Kenneth... floundering around with MMU unit test, no idea what...
2020-09-13 Luke Kenneth... mmu code-morph
2020-09-13 Luke Kenneth... code-morph, add masked function
2020-09-13 Luke Kenneth... move code to mmu_0
2020-09-13 Luke Kenneth... add example radix walk from power-gem5
2020-09-13 Luke Kenneth... MMU test
2020-09-13 Luke Kenneth... submodule update
2020-09-13 Luke Kenneth... clarify
2020-09-13 Luke Kenneth... sort out ariane PLRU, rename/clarify
2020-09-13 Luke Kenneth... minor error in plru
2020-09-13 Luke Kenneth... rename cache_valid_bits to cache_validsg
2020-09-13 Luke Kenneth... cache_valid_idx too large in dcache
2020-09-13 Luke Kenneth... whoops, cache valid array too small in dcache
2020-09-12 Luke Kenneth... more dcache debugging
2020-09-12 Luke Kenneth... missing reservation address comparison
2020-09-12 Luke Kenneth... dcache tidyup
2020-09-12 Luke Kenneth... more dcache debugging
2020-09-12 Luke Kenneth... add random dcache mem test
2020-09-12 Luke Kenneth... cache valid corrupted: fixed
2020-09-12 Luke Kenneth... adding names to array signals
2020-09-12 Luke Kenneth... whoops, indentation error
2020-09-12 Luke Kenneth... enable Display debugs
2020-09-12 Luke Kenneth... set bytesel in dcache store
2020-09-11 Luke Kenneth... separat stbs_done into ld/st
2020-09-11 Luke Kenneth... dcache load/store test
2020-09-11 Luke Kenneth... debugging dcache
2020-09-11 Luke Kenneth... wrong width for data / addr
2020-09-11 Luke Kenneth... connect up WB SRAM to dcache test
2020-09-11 Luke Kenneth... start on dcache test
2020-09-11 Luke Kenneth... missing comb +=
2020-09-11 Luke Kenneth... missing maybe_tlb_plrus
2020-09-11 Luke Kenneth... WAY_BITS not TLB_WAY_BITS
2020-09-11 Luke Kenneth... whoops new node not to be calculated at end
2020-09-11 Luke Kenneth... try to get better DTLBUpdate
2020-09-11 Luke Kenneth... simplify dcache pending
2020-09-11 Luke Kenneth... move dcache pending test to separate module
2020-09-11 Luke Kenneth... more error correction in dcache
2020-09-11 Luke Kenneth... use module for TLBUpdate
2020-09-11 Luke Kenneth... add brackets round if & in dcache
2020-09-11 Cole Poiriericache.py add test_icache and icache_sim derived from...
2020-09-11 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-09-11 Cole Poiriericache.py fix spelling, syntax
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