2020-09-17 |
Jacob Lifshay | replace sim._state.timeline.now with sim._engine.now |
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2020-09-17 |
Luke Kenneth... | add versa ecp5 fpga litex build script |
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2020-09-16 |
Cole Poirier | complete first translation pass of dmi_dtm_xilinx.vhdl... |
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2020-09-16 |
Luke Kenneth... | make a start on LS180 platform |
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2020-09-16 |
Cole Poirier | initial commit of JTAGToDMI debug interface translated... |
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2020-09-16 |
Cole Poirier | add template file/starting point (copy of litex/boards... |
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2020-09-15 |
Luke Kenneth... | add back (totally confusing) accidentally-removed code... |
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2020-09-15 |
Luke Kenneth... | instantiate MMU from AllFunctionUnits |
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2020-09-15 |
Luke Kenneth... | do not need FAST regs in MMU |
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2020-09-15 |
Luke Kenneth... | comment mmu test |
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2020-09-15 |
Luke Kenneth... | add edge-triggering to dcache/mmu "valid" |
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2020-09-15 |
Luke Kenneth... | add set MTSPR prtbl to mmu unit test |
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2020-09-15 |
Luke Kenneth... | add OP_MFSPR to mmu |
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2020-09-15 |
Luke Kenneth... | use convenience vars |
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2020-09-15 |
Luke Kenneth... | add OP_TLBIE to mmu fsm |
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2020-09-15 |
Luke Kenneth... | add OP_DCBZ to mmu fsm, needs RA to be added to MMU... |
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2020-09-15 |
Luke Kenneth... | add MMU MTSPR connection into FSM |
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2020-09-15 |
Luke Kenneth... | add in MMU and DCache into MMU FSM |
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2020-09-15 |
Luke Kenneth... | moved PLRU to nmutil |
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2020-09-15 |
Luke Kenneth... | add mmu fsm |
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2020-09-15 |
Luke Kenneth... | remove more (confusing/spurious) types, should be in... |
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2020-09-15 |
Luke Kenneth... | remove more (confusing/spurious) types, should be in... |
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2020-09-15 |
Luke Kenneth... | remove more (confusing/spurious) types, should be in... |
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2020-09-15 |
Luke Kenneth... | removed (confusing/spurious) types, should be in .pyi... |
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2020-09-15 |
Luke Kenneth... | add MMU FunctionUnit |
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2020-09-15 |
Luke Kenneth... | mmu uses RB, go with it |
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2020-09-15 |
Luke Kenneth... | add OP_TLBIE |
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2020-09-15 |
Luke Kenneth... | add mmu initial pipe_data.py |
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2020-09-15 |
Luke Kenneth... | add extra "modes" to PortInterface |
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2020-09-15 |
Luke Kenneth... | syntax error correction |
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2020-09-15 |
Luke Kenneth... | add inline comments into icache.py |
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2020-09-14 |
Cole Poirier | icache.py add missing funciton bodies, add missing... |
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2020-09-14 |
Luke Kenneth... | increase TLB_NUM_WAYS to 4 |
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2020-09-14 |
Luke Kenneth... | vhdl conversion not really working for plru |
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2020-09-14 |
Luke Kenneth... | add array signal names |
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2020-09-14 |
Luke Kenneth... | rename plru input |
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2020-09-14 |
Luke Kenneth... | rename plru input |
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2020-09-14 |
Luke Kenneth... | reorg mmu lookup test so it is called twice |
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2020-09-14 |
Luke Kenneth... | TLB PLRUs are of TLB_WAY_BITS width |
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2020-09-14 |
Luke Kenneth... | fix mmu perms/lookup in dcache |
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2020-09-14 |
Luke Kenneth... | whitespace |
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2020-09-14 |
Luke Kenneth... | remove duplicated signal |
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2020-09-14 |
Luke Kenneth... | comments on icache |
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2020-09-14 |
Luke Kenneth... | get rid of rst |
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2020-09-14 |
Luke Kenneth... | use word_select |
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2020-09-14 |
Luke Kenneth... | add mmu-dcache test |
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2020-09-14 |
Cole Poirier | icache.py connect up all the sub-functions, fix typos... |
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2020-09-14 |
Cole Poirier | icache.py add parameters to 'process' functions, fix... |
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2020-09-13 |
Cole Poirier | icache.py move get/read/write functions out of ICache... |
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2020-09-13 |
Cole Poirier | icache.py copy simulation code from dcache.py, fix... |
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2020-09-13 |
Cole Poirier | icache.py fix syntax, move all constants and Array... |
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2020-09-13 |
Cole Poirier | icache.py fix syntax errors that occured when running... |
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2020-09-13 |
Luke Kenneth... | dcache truncate wishbone address, store real_addr in... |
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2020-09-13 |
Luke Kenneth... | last mmu get seems ok |
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2020-09-13 |
Luke Kenneth... | whoops recursion error v.shift calculated from v.shift |
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2020-09-13 |
Luke Kenneth... | more experimenting with mmu READ_WAIT state |
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2020-09-13 |
Luke Kenneth... | radix tree wait error, investigating |
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2020-09-13 |
Luke Kenneth... | mmu test starting to make sense |
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2020-09-13 |
Luke Kenneth... | floundering around with MMU unit test, no idea what... |
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2020-09-13 |
Luke Kenneth... | mmu code-morph |
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2020-09-13 |
Luke Kenneth... | code-morph, add masked function |
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2020-09-13 |
Luke Kenneth... | move code to mmu_0 |
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2020-09-13 |
Luke Kenneth... | add example radix walk from power-gem5 |
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2020-09-13 |
Luke Kenneth... | MMU test |
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2020-09-13 |
Luke Kenneth... | submodule update |
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2020-09-13 |
Luke Kenneth... | clarify |
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2020-09-13 |
Luke Kenneth... | sort out ariane PLRU, rename/clarify |
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2020-09-13 |
Luke Kenneth... | minor error in plru |
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2020-09-13 |
Luke Kenneth... | rename cache_valid_bits to cache_validsg |
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2020-09-13 |
Luke Kenneth... | cache_valid_idx too large in dcache |
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2020-09-13 |
Luke Kenneth... | whoops, cache valid array too small in dcache |
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2020-09-12 |
Luke Kenneth... | more dcache debugging |
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2020-09-12 |
Luke Kenneth... | missing reservation address comparison |
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2020-09-12 |
Luke Kenneth... | dcache tidyup |
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2020-09-12 |
Luke Kenneth... | more dcache debugging |
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2020-09-12 |
Luke Kenneth... | add random dcache mem test |
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2020-09-12 |
Luke Kenneth... | cache valid corrupted: fixed |
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2020-09-12 |
Luke Kenneth... | adding names to array signals |
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2020-09-12 |
Luke Kenneth... | whoops, indentation error |
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2020-09-12 |
Luke Kenneth... | enable Display debugs |
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2020-09-12 |
Luke Kenneth... | set bytesel in dcache store |
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2020-09-11 |
Luke Kenneth... | separat stbs_done into ld/st |
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2020-09-11 |
Luke Kenneth... | dcache load/store test |
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2020-09-11 |
Luke Kenneth... | debugging dcache |
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2020-09-11 |
Luke Kenneth... | wrong width for data / addr |
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2020-09-11 |
Luke Kenneth... | connect up WB SRAM to dcache test |
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2020-09-11 |
Luke Kenneth... | start on dcache test |
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2020-09-11 |
Luke Kenneth... | missing comb += |
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2020-09-11 |
Luke Kenneth... | missing maybe_tlb_plrus |
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2020-09-11 |
Luke Kenneth... | WAY_BITS not TLB_WAY_BITS |
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2020-09-11 |
Luke Kenneth... | whoops new node not to be calculated at end |
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2020-09-11 |
Luke Kenneth... | try to get better DTLBUpdate |
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2020-09-11 |
Luke Kenneth... | simplify dcache pending |
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2020-09-11 |
Luke Kenneth... | move dcache pending test to separate module |
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2020-09-11 |
Luke Kenneth... | more error correction in dcache |
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2020-09-11 |
Luke Kenneth... | use module for TLBUpdate |
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2020-09-11 |
Luke Kenneth... | add brackets round if & in dcache |
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2020-09-11 |
Cole Poirier | icache.py add test_icache and icache_sim derived from... |
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2020-09-11 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-09-11 |
Cole Poirier | icache.py fix spelling, syntax |
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