riscv-isa-sim.git
2018-10-01 Luke Kenneth... whoops vloop continuation logic the wrong way round
2018-10-01 Luke Kenneth... skip parallelisation of complex LR/SC operations
2018-10-01 Luke Kenneth... identify type of instruction with additional #defines
2018-09-30 Luke Kenneth... add a #define to id_regs.py which indicates name of...
2018-09-30 Luke Kenneth... list of instructions to avoid parallelising
2018-09-30 Luke Kenneth... update template comment
2018-09-30 Luke Kenneth... lots of debugging of predication, found other errors
2018-09-30 Luke Kenneth... add sv support for zeroing predication in dest register
2018-09-30 Luke Kenneth... add in predication to sv instruction execution
2018-09-30 Luke Kenneth... start linking in predication into sv
2018-09-30 Luke Kenneth... use an alternative logic for detecting scalar / loop-end
2018-09-30 Luke Kenneth... add compressed-identifying patterns to id_regs.py
2018-09-30 Luke Kenneth... fix code template for when SPIKE_SIMPLEV is not defined
2018-09-30 Luke Kenneth... yuk. break id_regs.py being a generic tool by skipping...
2018-09-29 Luke Kenneth... fix bug in sv template where FRS2 was checking rs3
2018-09-29 Luke Kenneth... add checks for RVC registers to sv template
2018-09-29 Luke Kenneth... add sv_insn_t overloads for rvc registers
2018-09-29 Luke Kenneth... also arrange for id_regs.py to identify compressed...
2018-09-29 Luke Kenneth... a LOT of debugging and fixing, sv loop actually working
2018-09-29 Luke Kenneth... move SV CSRs to user-read-write
2018-09-29 Luke Kenneth... add near-duplicate of SV CFG REG CSRs, for predication
2018-09-29 Luke Kenneth... add implementation of CSR SV CFG regs 0-7
2018-09-29 Luke Kenneth... assign SV REG CSRs (using new union ability)
2018-09-29 Luke Kenneth... make sv csr tables a union so they can be assigned...
2018-09-29 Luke Kenneth... add support for CSR_SVVL to CSRRWI as well
2018-09-29 Luke Kenneth... fix bug in CSR set SVVL: val has already been looked up
2018-09-29 Luke Kenneth... add stub for SV REG configs
2018-09-29 Luke Kenneth... stop a compiler warning
2018-09-29 Luke Kenneth... reorganise from moving sv_pred_* and sv_reg_* tables...
2018-09-29 Luke Kenneth... have to move SV CSRs into processor_t
2018-09-29 Luke Kenneth... add 8 CSRs for registers and predication each
2018-09-29 Luke Kenneth... whoops dont need separate SVSETVL/SVGETVL CSRs
2018-09-29 Luke Kenneth... revert addition of svsetvl as an actual opcode, add...
2018-09-29 Luke Kenneth... Revert "sv setvl as a csr not going to work, add getvl...
2018-09-29 Luke Kenneth... Revert "manually add svsetvl instruction"
2018-09-28 Luke Kenneth... manually add svsetvl instruction
2018-09-28 Luke Kenneth... sv setvl as a csr not going to work, add getvl only
2018-09-27 Luke Kenneth... adding sv vector length CSR to processor state, and...
2018-09-27 Luke Kenneth... add sv predication function
2018-09-26 Luke Kenneth... save some cpu cycles by |ing the checks for vectorop...
2018-09-26 Luke Kenneth... whoops vectorop has to be |= not &= to accumulate ...
2018-09-26 Luke Kenneth... cache the sv redirected register values on each loop
2018-09-26 Luke Kenneth... remembered that the use of sv registers have to be...
2018-09-26 Luke Kenneth... clarify comments on (key strategic) sv_insn_t::remap...
2018-09-26 Luke Kenneth... actually implement sv register re-mapping
2018-09-26 Luke Kenneth... ok this is tricky: an extra parameter has to be passed...
2018-09-26 Luke Kenneth... move sv remap function to sv.cc (not inline)
2018-09-26 Luke Kenneth... check if register redirection is active, and if vectori...
2018-09-26 Luke Kenneth... comment why sv_insn_t is set up the way it is; add...
2018-09-26 Luke Kenneth... easier to #define USING_NOREGS if the opcode does not...
2018-09-26 Luke Kenneth... include auto-generated identification of use of registe...
2018-09-26 Luke Kenneth... shuffle things around a bit for sv, put rv32/64_name...
2018-09-25 Luke Kenneth... skip id_reg.py parsing its own output; stop outputting...
2018-09-25 Luke Kenneth... change to instruction template parsing, create one...
2018-09-25 Luke Kenneth... add decode.h header to sv.h
2018-09-25 Luke Kenneth... rename sv vlen to sv voffs, add csr and reg tables
2018-09-25 Luke Kenneth... add reference to vector length in sv
2018-09-25 Luke Kenneth... use sv_insn_t class in instruction template
2018-09-25 Luke Kenneth... add sv_insn_t class (inherits from insn_t)
2018-09-25 Luke Kenneth... argh cant virtualise rd/rs1-3, due to union usage with...
2018-09-25 Luke Kenneth... sv: rd, rs1/2/3 become virtual so that sv_insn_t can...
2018-09-25 Luke Kenneth... clarify sv cam table
2018-09-24 Luke Kenneth... define CSR and register tables for SV
2018-09-24 Luke Kenneth... remove unneeded use of AM_CONDITIONAL
2018-09-24 Luke Kenneth... add #define for SPIKE_SIMPLEV, re-run autoreconf
2018-09-24 Luke Kenneth... create #defines from identified registers, per opcode
2018-09-24 Luke Kenneth... clarify docstring on id_regs.py
2018-09-24 Luke Kenneth... add function identifying the registers in each emulated...
2018-09-24 Luke Kenneth... identify instructions, plan: extract registers
2018-09-13 Andrew WatermanUpdate README master
2018-09-06 Tim NewsomeMerge pull request #235 from riscv/sba
2018-09-05 Tim NewsomeFix cut-and-paste bug in 64-bit SBA loads.
2018-08-24 Andrew WatermanHandle spike-dasm inputs with leading 0x correctly
2018-08-24 Tim NewsomeAdd dummy custom debug registers, to test OpenOCD....
2018-08-24 Andrew WatermanFix several disassembler bugs
2018-08-23 Andrew WatermanAdd --disable-dtb option to suppress writing the DTB...
2018-08-22 Andrew WatermanMake IRQ_COP read-only/undelegable unless coprocessor...
2018-08-21 Andrew WatermanInstantiate disassembler after max_xlen is known
2018-08-18 Andrew WatermanDon't increment instret immediately after it is written...
2018-08-10 Tim NewsomeFix 2 trigger corner cases. (#229)
2018-07-31 Andrew WatermanMake sstatus.MXR readable
2018-07-23 SeungRyeol LeeFix using the uninitialized disassemble object. (#220)
2018-07-10 Andrew WatermanRefactor and fix LR/SC implementation (#217)
2018-06-12 Tim NewsomeMerge pull request #212 from riscv/hartsel
2018-06-11 Tim NewsomeUpdate debug_defines.h
2018-05-31 Andy WrightPut simif_t declaration in its own file. (#209)
2018-05-18 Prashanth MundkurFix install of missed header. (#207)
2018-05-18 Prashanth MundkurExtract out device-tree generation and compilation...
2018-05-04 Andrew WatermanRevert "C.LWSP and C.LDSP with rd=0 are legal instructions"
2018-05-04 Andrew WatermanC.LWSP and C.LDSP with rd=0 are legal instructions
2018-05-01 Andrew WatermanFix commit log for serializing instructions
2018-04-30 Andrew WatermanOnly break out of the simulator loop on WFI, not on...
2018-04-29 Andrew WatermanWhen no arguments are passed, print spike help, not...
2018-04-05 Prashanth MundkurAllow querying the mmu configuration chosen during...
2018-04-04 Andrew WatermanRevert "Fix for issue #183: No illegal instruction...
2018-03-30 Palmer DabbeltMerge pull request #189 from pmundkur/pm-csr-name-api
2018-03-26 Prashanth MundkurAdd an api to get the name for a CSR.
2018-03-22 Andrew WatermanImplement Hauser misa.C misalignment proposal (#187)
2018-03-21 Prashanth MundkurFix the access exception during page-table walks to...
2018-03-19 Tim NewsomeFix spike-dasm. (#184)
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