Add count leading zeros module (should probably go somewhere else)
[ieee754fpu.git] / src / ieee754 / cordic / test /
drwxr-xr-x   ..
-rw-r--r-- 745 python_sin_cos.py
-rw-r--r-- 966 test_clz.py
-rw-r--r-- 1857 test_fp_pipe.py
-rw-r--r-- 2949 test_fpsin_cos.py
-rw-r--r-- 2272 test_sincos.py
-rw-r--r-- 864 test_software.py