projects / soc.git / tree
? search:
summary | shortlog | log | commit | commitdiff | tree
history | HEAD
set ROM to empty, set SRAM to tiny 0x200, get things working first
[soc.git] / src / soc / config /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py blob | history | raw
-rw-r--r-- 80 endian.py blob | history | raw
-rw-r--r-- 795 ifetch.py blob | history | raw
-rw-r--r-- 1733 loadstore.py blob | history | raw
-rw-r--r-- 429 state.py blob | history | raw
drwxr-xr-x - test tree | history