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DMI-to-JTAG needed to be "sync" to get ack/resp right
[soc.git] / src / soc / config /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py blob | history | raw
-rw-r--r-- 80 endian.py blob | history | raw
-rw-r--r-- 795 ifetch.py blob | history | raw
-rw-r--r-- 1733 loadstore.py blob | history | raw
-rw-r--r-- 429 state.py blob | history | raw
drwxr-xr-x - test tree | history