add srcstep and correct PC-advancing during Sub-PC looping in ISACaller
[soc.git] / src / soc / fu /
drwxr-xr-x   ..
-rw-r--r-- 4017 README.md
-rw-r--r-- 0 __init__.py
drwxr-xr-x - alu
-rw-r--r-- 1333 base_input_record.py
drwxr-xr-x - branch
-rw-r--r-- 2308 common_input_stage.py
-rw-r--r-- 3911 common_output_stage.py
drwxr-xr-x - compunits
drwxr-xr-x - cr
drwxr-xr-x - div
drwxr-xr-x - ldst
drwxr-xr-x - logical
drwxr-xr-x - mmu
drwxr-xr-x - mul
-rw-r--r-- 2483 pipe_data.py
-rw-r--r-- 3332 regspec.py
drwxr-xr-x - shift_rot
drwxr-xr-x - spr
drwxr-xr-x - test
drwxr-xr-x - trap