Removed extraneous variable from 'ports=[..]' of main in bperm.py
[soc.git] / src / soc / logical / formal /
drwxr-xr-x   ..
-rw-r--r-- 4 .gitignore
-rw-r--r-- 4772 proof_bperm.py
-rw-r--r-- 2403 proof_input_stage.py
-rw-r--r-- 2812 proof_main_stage.py