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fix syntax errors and use correct FastRegs (SRR0/1 not SRR1/2)
[soc.git]
/
src
/
soc
/
regfile
/
drwxr-xr-x
..
drwxr-xr-x
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regfile.py
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4563
regfiles.py
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298
util.py
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virtual_port.py
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projects / soc.git / tree