remove bitmanip fu cuz ternlogi (the only instruction implemented so far) is in shift...
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 48690 core.py
-rw-r--r-- 4568 core_data.py
-rw-r--r-- 64235 issuer.py
-rw-r--r-- 5101 issuer_verilog.py
drwxr-xr-x - test