Skip fetching integer predicate mask when register number is zero
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 22186 core.py
-rw-r--r-- 48622 issuer.py
-rw-r--r-- 3905 issuer_verilog.py
drwxr-xr-x - test