move over to from openpower imports
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 22808 core.py
-rw-r--r-- 55631 issuer.py
-rw-r--r-- 4913 issuer_verilog.py
drwxr-xr-x - test