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pass in CoreState to PowerDecoder rather than eq a copy of it
[soc.git]
/
src
/
soc
/
simple
/
drwxr-xr-x
..
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0
__init__.py
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-rw-r--r--
21467
core.py
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raw
-rw-r--r--
17322
issuer.py
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1200
issuer_verilog.py
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projects / soc.git / tree