sigh have to allow external clocks and reset mess even in microwatt-compat
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 51947 core.py
-rw-r--r-- 4618 core_data.py
-rw-r--r-- 22414 inorder.py
-rw-r--r-- 74791 issuer.py
-rw-r--r-- 6313 issuer_verilog.py
drwxr-xr-x - test