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replace data_o with o_data and data_i with i_data as well
[soc.git]
/
src
/
soc
/
simple
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drwxr-xr-x
..
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0
__init__.py
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24453
core.py
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60073
issuer.py
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5101
issuer_verilog.py
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projects / soc.git / tree