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underscore names on submodules possibly interfering with verilator
[c4m-jtag.git]
/
c4m
/
nmigen
/
jtag
/
tap.py
diff --git
a/c4m/nmigen/jtag/tap.py
b/c4m/nmigen/jtag/tap.py
index 41174a31f27fb99296dcf748d852fd768d5939ec..19902dc4768e8e51d19936e9294088e33388e99c 100755
(executable)
--- a/
c4m/nmigen/jtag/tap.py
+++ b/
c4m/nmigen/jtag/tap.py
@@
-361,13
+361,13
@@
class TAP(Elaboratable):
cmd_preload = 2
cmd_bypass = 2**ir_width - 1 # All ones
cmd_preload = 2
cmd_bypass = 2**ir_width - 1 # All ones
- m.submodules.
_
fsm = fsm = _FSM(bus=self.bus)
+ m.submodules.fsm = fsm = _FSM(bus=self.bus)
m.domains.posjtag = fsm.posjtag
m.domains.negjtag = fsm.negjtag
# IR block
select_ir = fsm.isir
m.domains.posjtag = fsm.posjtag
m.domains.negjtag = fsm.negjtag
# IR block
select_ir = fsm.isir
- m.submodules.
_
irblock = irblock = _IRBlock(
+ m.submodules.irblock = irblock = _IRBlock(
ir_width=ir_width, cmd_idcode=cmd_idcode, tdi=self.bus.tdi,
capture=(fsm.isir & fsm.capture),
shift=(fsm.isir & fsm.shift),
ir_width=ir_width, cmd_idcode=cmd_idcode, tdi=self.bus.tdi,
capture=(fsm.isir & fsm.capture),
shift=(fsm.isir & fsm.shift),
@@
-382,7
+382,7
@@
class TAP(Elaboratable):
m.d.comb += select_id.eq(fsm.isdr &
((ir == cmd_idcode) | (ir == cmd_bypass)))
m.d.comb += id_bypass.eq(ir == cmd_bypass)
m.d.comb += select_id.eq(fsm.isdr &
((ir == cmd_idcode) | (ir == cmd_bypass)))
m.d.comb += id_bypass.eq(ir == cmd_bypass)
- m.submodules.
_
idblock = idblock = _IDBypassBlock(
+ m.submodules.idblock = idblock = _IDBypassBlock(
manufacturer_id=self._manufacturer_id,
part_number=self._part_number,
version=self._version, tdi=self.bus.tdi,
manufacturer_id=self._manufacturer_id,
part_number=self._part_number,
version=self._version, tdi=self.bus.tdi,