Merge branch 'upstream_libresoc' into libresoc_master

[c4m-jtag.git] / c4m / nmigen / jtag / tap.py

diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py
index a72c89a0956f25b41e9fb10ed088f3844afd0b84..1f3d424cbd7451c0434e0c71168f5aa0935af860 100755 (executable)
--- a/c4m/nmigen/jtag/tap.py
+++ b/c4m/nmigen/jtag/tap.py
@@ -662,6 +662,9 @@ class TAP(Elaboratable):
             # clockdomain latch update in `domain` clockdomain and see when
             # it has falling edge.
             # At that edge put isir in sr.oe for one `domain` clockdomain
+            # Using this custom sync <> JTAG domain synchronization avoids
+            # the use of more generic but also higher latency CDC solutions
+            # like FFSynchronizer.
             update_core = Signal(name=sr.name+"_update_core")
             update_core_prev = Signal(name=sr.name+"_update_core_prev")
             m.d[domain] += [
@@ -777,7 +780,10 @@ class TAP(Elaboratable):
                 with m.State("READACK"):
                     with m.If(wb.ack):
                         # Store read data in sr_data.i
-                        # and keep it there til next read
+                        # and keep it there til next read.
+                        # This is enough to synchronize between sync and JTAG
+                        # clock domain and no higher latency solutions like
+                        # FFSynchronizer is needed.
                         m.d[domain] += sr_data.i.eq(wb.dat_r)
                         m.next = "IDLE"
                 with m.State("WRITEREAD"):