Force passing by name for TAP.add_shiftreg().

[c4m-jtag.git] / c4m / nmigen / jtag / tap.py

diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py
index fdcf762b8d58e220bb59b9a6a51b5fb9129a13d7..b2bcf818f8a3a2bc5b9fe62bfa5dafd628b8321b 100755 (executable)
--- a/c4m/nmigen/jtag/tap.py
+++ b/c4m/nmigen/jtag/tap.py
@@ -97,9 +97,9 @@ class TAP(Elaboratable):
     
         -- The FSM state indicators
         RESET:      out std_logic;
-        DRCAPTURE:  out std_logic;
-        DRSHIFT:    out std_logic;
-        DRUPDATE:   out std_logic;
+        CAPTURE:    out std_logic;
+        SHIFT:      out std_logic;
+        UPDATE:     out std_logic;
     
         -- The Instruction Register
         IR:         out std_logic_vector({ir_width}-1 downto 0);
@@ -134,9 +134,9 @@ class TAP(Elaboratable):
           TDO => TDO,
           TRST_N => TRST_N,
           RESET => RESET,
-          DRCAPTURE => DRCAPTURE,
-          DRSHIFT => DRSHIFT,
-          DRUPDATE => DRUPDATE,
+          CAPTURE => CAPTURE,
+          SHIFT => SHIFT,
+          UPDATE => UPDATE,
           IR => IR,
           CORE_IN => CORE_IN,
           CORE_EN => CORE_EN,
@@ -174,13 +174,21 @@ class TAP(Elaboratable):
         assert((ir_width is None) or (isinstance(ir_width, int) and ir_width >= 2))
         assert(len(version) == 4)
 
-        self.name = name if name is not None else get_var_name(depth=src_loc_at+2, default="TAP")
+        if name is None:
+            name = get_var_name(depth=src_loc_at+2, default="TAP")
+        self.name = name
         self.bus = Interface(with_reset=with_reset, name=self.name+"_bus",
                              src_loc_at=src_loc_at+1)
 
         # TODO: Handle IOs with different directions
-        self.core = Array(Pin(1, "io") for _ in range(io_count)) # Signals to use for core
-        self.pad  = Array(Pin(1, "io") for _ in range(io_count)) # Signals going to IO pads
+        self.core = Array(
+            Pin(1, "io", name=name+"_coreio"+str(i), src_loc_at=src_loc_at+1)
+            for i in range(io_count)
+        ) # Signals to use for core
+        self.pad  = Array(
+            Pin(1, "io", name=name+"_padio"+str(i), src_loc_at=src_loc_at+1)
+            for i in range(io_count)
+        ) # Signals going to IO pads
 
         ##
 
@@ -266,7 +274,7 @@ class TAP(Elaboratable):
         return m
 
 
-    def add_shiftreg(self, ircode, length, domain="sync", name=None, src_loc_at=0):
+    def add_shiftreg(self, *, ircode, length, domain="sync", name=None, src_loc_at=0):
         """Add a shift register to the JTAG interface
 
         Parameters: