core: subrecord with signals for the core
i: Signal(1), present only for IOType.In and IOType.InTriOut.
Signal input to core with pad input value.
core: subrecord with signals for the core
i: Signal(1), present only for IOType.In and IOType.InTriOut.
Signal input to core with pad input value.
Signal output from core with the pad output value.
oe: Signal(1), present only for IOType.TriOut and IOType.InTriOut.
Signal output from core with the pad output enable value.
pad: subrecord with for the pad
i: Signal(1), present only for IOType.In and IOType.InTriOut
Output from pad with pad input value for core.
Signal output from core with the pad output value.
oe: Signal(1), present only for IOType.TriOut and IOType.InTriOut.
Signal output from core with the pad output enable value.
pad: subrecord with for the pad
i: Signal(1), present only for IOType.In and IOType.InTriOut
Output from pad with pad input value for core.
Input to pad with pad output value.
oe: Signal(1), present only for IOType.TriOut and IOType.InTriOut.
Input to pad with pad output enable value.
Input to pad with pad output value.
oe: Signal(1), present only for IOType.TriOut and IOType.InTriOut.
Input to pad with pad output enable value.
return Layout((("core", sigs), ("pad", sigs)))
def __init__(self, *, iotype, name=None, src_loc_at=0):
return Layout((("core", sigs), ("pad", sigs)))
def __init__(self, *, iotype, name=None, src_loc_at=0):
- super().__init__(self.__class__.layout(iotype), name=name, src_loc_at=src_loc_at+1)
+ super().__init__(self.__class__.layout(iotype), name=name,
+ src_loc_at=src_loc_at+1)
tdi, capture, shift, update, bypass,
name):
self.name = name
tdi, capture, shift, update, bypass,
name):
self.name = name
raise ValueError("manufacturer_id has to be Const of length 11")
if not isinstance(part_number, Const) and len(manufacturer_id) != 16:
raise ValueError("part_number has to be Const of length 16")
raise ValueError("manufacturer_id has to be Const of length 11")
if not isinstance(part_number, Const) and len(manufacturer_id) != 16:
raise ValueError("part_number has to be Const of length 16")
- self._ircodes = [0, 1, 2] # Already taken codes, all ones added at the end
+ self._ircodes = [0, 1, 2] # Already taken codes, all ones added at end
ir_max = max(self._ircodes) + 1 # One extra code needed with all ones
ir_width = len("{:b}".format(ir_max))
if self._ir_width is not None:
ir_max = max(self._ircodes) + 1 # One extra code needed with all ones
ir_width = len("{:b}".format(ir_max))
if self._ir_width is not None:
- assert self._ir_width >= ir_width, "Specified JTAG IR width not big enough for allocated shiift registers"
+ assert self._ir_width >= ir_width, "Specified JTAG IR width " \
+ "not big enough for allocated shiift registers"
# ID block
select_id = fsm.isdr & ((ir == cmd_idcode) | (ir == cmd_bypass))
m.submodules._idblock = idblock = _IDBypassBlock(
# ID block
select_id = fsm.isdr & ((ir == cmd_idcode) | (ir == cmd_bypass))
m.submodules._idblock = idblock = _IDBypassBlock(
- manufacturer_id=self._manufacturer_id, part_number=self._part_number,
+ manufacturer_id=self._manufacturer_id,
+ part_number=self._part_number,
version=self._version, tdi=self.bus.tdi,
capture=(select_id & fsm.capture),
shift=(select_id & fsm.shift),
version=self._version, tdi=self.bus.tdi,
capture=(select_id & fsm.capture),
shift=(select_id & fsm.shift),
io_shift.eq(select_io & fsm.shift),
io_update.eq(select_io & fsm.update),
io_bd2io.eq(ir == cmd_extest),
io_shift.eq(select_io & fsm.shift),
io_update.eq(select_io & fsm.update),
io_bd2io.eq(ir == cmd_extest),
- def add_shiftreg(self, *, ircode, length, domain="sync", name=None, src_loc_at=0):
+ def add_shiftreg(self, *, ircode, length, domain="sync", name=None,
+ src_loc_at=0):
- - ircode: code(s) for the IR; int or sequence of ints. In the latter case this
- shiftreg is shared between different IR codes.
+ - ircode: code(s) for the IR; int or sequence of ints. In the latter
+ case this shiftreg is shared between different IR codes.
ir_it = ircodes = (ircode,)
for _ircode in ir_it:
if not isinstance(_ircode, int) or _ircode <= 0:
ir_it = ircodes = (ircode,)
for _ircode in ir_it:
if not isinstance(_ircode, int) or _ircode <= 0:
- sr = ShiftReg(sr_length=length, cmds=len(ircodes), name=name, src_loc_at=src_loc_at+1)
+ sr = ShiftReg(sr_length=length, cmds=len(ircodes), name=name,
+ src_loc_at=src_loc_at+1)
- # update signal is on the JTAG clockdomain, sr.oe is on `domain` clockdomain
- # latch update in `domain` clockdomain and see when it has falling edge.
+ # update signal is on the JTAG clockdomain, sr.oe is on `domain`
+ # clockdomain latch update in `domain` clockdomain and see when
+ # it has falling edge.
- # Using this custom sync <> JTAG domain synchronization avoids the use of
- # more generic but also higher latency CDC solutions like FFSynchronizer.
+ # Using this custom sync <> JTAG domain synchronization avoids
+ # the use of more generic but also higher latency CDC solutions
+ # like FFSynchronizer.
update_core = Signal(name=sr.name+"_update_core")
update_core_prev = Signal(name=sr.name+"_update_core_prev")
m.d[domain] += [
update_core = Signal(name=sr.name+"_update_core")
update_core_prev = Signal(name=sr.name+"_update_core_prev")
m.d[domain] += [
- def add_wishbone(self, *, ircodes, address_width, data_width, granularity=None, domain="sync",
+ def add_wishbone(self, *, ircodes, address_width, data_width,
+ granularity=None, domain="sync",
name=None, src_loc_at=0):
"""Add a wishbone interface
name=None, src_loc_at=0):
"""Add a wishbone interface
- In order to allow high JTAG clock speed, data will be cached. This means that if data is
- output the value of the next address will be read automatically.
+ In order to allow high JTAG clock speed, data will be cached.
+ This means that if data is output the value of the next address
+ will be read automatically.
- granularity=granularity, features={"stall", "lock", "err", "rty"},
+ granularity=granularity,
+ features={"stall", "lock", "err", "rty"},
name=name, src_loc_at=src_loc_at+1)
self._wbs.append((sr_addr, sr_data, wb, domain))
name=name, src_loc_at=src_loc_at+1)
self._wbs.append((sr_addr, sr_data, wb, domain))
- # Store read data in sr_data.i and keep it there til next read
- # This is enough to synchronize between sync and JTAG clock domain
- # and no higher latency solutions like FFSynchronizer is needed.
+ # Store read data in sr_data.i
+ # and keep it there til next read.
+ # This is enough to synchronize between sync and JTAG
+ # clock domain and no higher latency solutions like
+ # FFSynchronizer is needed.