do not need to do IOconn

diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py
index 73541df323c70b0a83b682293c1924fb59506497..af27add3b45805e18d7d9950778790eff246f643 100755 (executable)
--- a/c4m/nmigen/jtag/tap.py
+++ b/c4m/nmigen/jtag/tap.py
@@ -412,8 +412,9 @@ class TAP(Elaboratable):
             m.d.comb += tdo.eq(irblock.tdo)
         with m.Elif(select_id):
             m.d.comb += tdo.eq(idblock.tdo)
-        with m.Elif(select_io):
-            m.d.comb += tdo.eq(io_tdo)
+        if io_tdo is not None:
+            with m.Elif(select_io):
+                m.d.comb += tdo.eq(io_tdo)
 
         # shiftregs block
         self._elaborate_shiftregs(
@@ -594,8 +595,8 @@ class TAP(Elaboratable):
                 raise("Internal error")
         assert idx == length, "Internal error"
 
-        return io_sr[-1]
-
+        if io_sr:
+            return io_sr[-1]
 
     def add_shiftreg(self, *, ircode, length, domain="sync", name=None,
                      src_loc_at=0):