separate section for meeting

[crowdsupply.git] / updates / 021_2019dec29_nlnet_grants_approved.mdwn

diff --git a/updates/021_2019dec29_nlnet_grants_approved.mdwn b/updates/021_2019dec29_nlnet_grants_approved.mdwn
index e11ea6cbe3251afd5d0e613e42085bc7731a3097..0a57d80ef6429416591fc84a26cc4b2bf3f6b5df 100644 (file)
--- a/updates/021_2019dec29_nlnet_grants_approved.mdwn
+++ b/updates/021_2019dec29_nlnet_grants_approved.mdwn
@@ -25,18 +25,17 @@ expand on the core, to cover:
 * a Wishbone streaming enhancement to add A/V timecode stamps to Wishbone B4,
   and to develop independent libre-licensed peripherals as examples
 * two interrelated proposals to develop libre cell Libraries
-  ([Chips4Makers](http://chips4makers.be)), to be used by a team at
+  ([Chips4Makers](http://chips4makers.io/)), to be used by a team at
   [LIP6.fr](http://lip6.fr) using the Alliance / Coriolis2 ASIC layout
   tools; Additional funding will go to the nmigen team for ASIC
   improvements and special integration with Coriolis2
 
-The goal here is to get to a working, commercially viable 180 nm single-core
-ASIC at around 300 to 350 MHz, suitable for use as a high-end embedded
-controller.  Staf from Chips4Makers will act as the "NDA firebreak" between
-us and TSMC.
-(side-note: Staf ran a
-[Crowdsupply](https://www.crowdsupply.com/chips4makers/retro-uc)
-campaign, and the NLNet funding will help him to realise that project and
+The goal here is to get to a working, commercially viable 180 nm
+single-core ASIC at around 300 to 350 MHz, suitable for use as a
+high-end embedded controller.  Staf from Chips4Makers will act as the
+"NDA firebreak" between us and TSMC.  (Side note: Staf ran a [Crowd
+Supply campaign](https://www.crowdsupply.com/chips4makers/retro-uc),
+and the NLNet funding will help him to realise that project and
 perhaps re-start a new campaign for the Retro-uC one day).
 
 All of these have been approved by NLNet, and, crucially, the external
@@ -169,13 +168,13 @@ with a *userspace* RV64GC dual-ISA front-end.  **Userspace** RISC-V POSIX
 PowerISA POSIX applications, however the **kernel** (supervisor) space will
 be entirely PowerISA.
 
-The video and 3D acceleration opcodes will be **entirely in the Power ISA**.
-We are sick and tired of the RISC-V Foundation's blatant mismanagement.
-Therefore, we will comply to the absolute minimal letter with RV64GC for
-the benefit of our users, backers, and sponsors. However, RISC-V and the
-RISC-V ISA itself
-will no longer receive the benefit of the advancements and innovation
-that we have received funding and support to develop.
+The video and 3D acceleration opcodes will be **entirely in the Power
+ISA**.  We are sick and tired of the RISC-V Foundation's intransigence
+and blatant mismanagement.  Therefore, we will comply to the absolute
+minimal letter with RV64GC for the benefit of our users, backers, and
+sponsors who will be expecting RISC-V Compliance.  However, RISC-V and the
+RISC-V ISA itself will no longer receive the benefit of the advancements
+and innovation that we have received funding and support to develop.
 
 So, the assembly-code being written by hand for the video acceleration
 side, as well as the 3D drivers for Kazan and MESA, will "flip" from RV64GC