src/main/scala/unleashed/u500vc707devkit/System.scala

   1 // See LICENSE for license details.
   2 package sifive.freedom.unleashed.u500vc707devkit
   3
   4 import Chisel._
   5
   6 import freechips.rocketchip.config._
   7 import freechips.rocketchip.coreplex._
   8 import freechips.rocketchip.devices.debug._
   9 import freechips.rocketchip.devices.tilelink._
  10 import freechips.rocketchip.diplomacy._
  11 import freechips.rocketchip.system._
  12
  13 import sifive.blocks.devices.gpio._
  14 import sifive.blocks.devices.spi._
  15 import sifive.blocks.devices.uart._
  16
  17 import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
  18 import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
  19
  20 //-------------------------------------------------------------------------
  21 // U500VC707DevKitSystem
  22 //-------------------------------------------------------------------------
  23
  24 class U500VC707DevKitSystem(implicit p: Parameters) extends RocketCoreplex
  25     with HasPeripheryMaskROMSlave
  26     with HasPeripheryDebug
  27     with HasSystemErrorSlave
  28     with HasPeripheryUART
  29     with HasPeripherySPI
  30     with HasPeripheryGPIO
  31     with HasMemoryXilinxVC707MIG
  32     with HasSystemXilinxVC707PCIeX1 {
  33   override lazy val module = new U500VC707DevKitSystemModule(this)
  34 }
  35
  36 class U500VC707DevKitSystemModule[+L <: U500VC707DevKitSystem](_outer: L)
  37   extends RocketCoreplexModule(_outer)
  38     with HasRTCModuleImp
  39     with HasPeripheryDebugModuleImp
  40     with HasPeripheryUARTModuleImp
  41     with HasPeripherySPIModuleImp
  42     with HasPeripheryGPIOModuleImp
  43     with HasMemoryXilinxVC707MIGModuleImp
  44     with HasSystemXilinxVC707PCIeX1ModuleImp {
  45   // Reset vector is set to the location of the mask rom
  46   val maskROMParams = p(PeripheryMaskROMKey)
  47   global_reset_vector := maskROMParams(0).address.U
  48 }