1 # Copyright (c) 2012-2013 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2006-2008 The Regents of The University of Michigan
14 # Copyright (c) 2010 Advanced Micro Devices, Inc.
15 # All rights reserved.
17 # Redistribution and use in source and binary forms, with or without
18 # modification, are permitted provided that the following conditions are
19 # met: redistributions of source code must retain the above copyright
20 # notice, this list of conditions and the following disclaimer;
21 # redistributions in binary form must reproduce the above copyright
22 # notice, this list of conditions and the following disclaimer in the
23 # documentation and/or other materials provided with the distribution;
24 # neither the name of the copyright holders nor the names of its
25 # contributors may be used to endorse or promote products derived from
26 # this software without specific prior written permission.
28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 from __future__
import print_function
41 from __future__
import absolute_import
46 from os
.path
import join
as joinpath
48 from common
import CpuConfig
49 from common
import ObjectList
52 from m5
.defines
import buildEnv
53 from m5
.objects
import *
59 addToPath('../common')
61 def getCPUClass(cpu_type
):
62 """Returns the required cpu class and the mode of operation."""
63 cls
= ObjectList
.cpu_list
.get(cpu_type
)
64 return cls
, cls
.memory_mode()
66 def setCPUClass(options
):
67 """Returns two cpu classes and the initial mode of operation.
69 Restoring from a checkpoint or fast forwarding through a benchmark
70 can be done using one type of cpu, and then the actual
71 simulation can be carried out using another type. This function
72 returns these two types of cpus and the initial mode of operation
73 depending on the options provided.
76 TmpClass
, test_mem_mode
= getCPUClass(options
.cpu_type
)
78 if TmpClass
.require_caches() and \
79 not options
.caches
and not options
.ruby
:
80 fatal("%s must be used with caches" % options
.cpu_type
)
82 if options
.checkpoint_restore
!= None:
83 if options
.restore_with_cpu
!= options
.cpu_type
:
85 TmpClass
, test_mem_mode
= getCPUClass(options
.restore_with_cpu
)
86 elif options
.fast_forward
:
88 TmpClass
= AtomicSimpleCPU
89 test_mem_mode
= 'atomic'
91 # Ruby only supports atomic accesses in noncaching mode
92 if test_mem_mode
== 'atomic' and options
.ruby
:
93 warn("Memory mode will be changed to atomic_noncaching")
94 test_mem_mode
= 'atomic_noncaching'
96 return (TmpClass
, test_mem_mode
, CPUClass
)
98 def setMemClass(options
):
99 """Returns a memory controller class."""
101 return ObjectList
.mem_list
.get(options
.mem_type
)
103 def setWorkCountOptions(system
, options
):
104 if options
.work_item_id
!= None:
105 system
.work_item_id
= options
.work_item_id
106 if options
.num_work_ids
!= None:
107 system
.num_work_ids
= options
.num_work_ids
108 if options
.work_begin_cpu_id_exit
!= None:
109 system
.work_begin_cpu_id_exit
= options
.work_begin_cpu_id_exit
110 if options
.work_end_exit_count
!= None:
111 system
.work_end_exit_count
= options
.work_end_exit_count
112 if options
.work_end_checkpoint_count
!= None:
113 system
.work_end_ckpt_count
= options
.work_end_checkpoint_count
114 if options
.work_begin_exit_count
!= None:
115 system
.work_begin_exit_count
= options
.work_begin_exit_count
116 if options
.work_begin_checkpoint_count
!= None:
117 system
.work_begin_ckpt_count
= options
.work_begin_checkpoint_count
118 if options
.work_cpus_checkpoint_count
!= None:
119 system
.work_cpus_ckpt_count
= options
.work_cpus_checkpoint_count
121 def findCptDir(options
, cptdir
, testsys
):
122 """Figures out the directory from which the checkpointed state is read.
124 There are two different ways in which the directories holding checkpoints
126 1. cpt.<benchmark name>.<instruction count when the checkpoint was taken>
127 2. cpt.<some number, usually the tick value when the checkpoint was taken>
129 This function parses through the options to figure out which one of the
130 above should be used for selecting the checkpoint, and then figures out
131 the appropriate directory.
134 from os
.path
import isdir
, exists
135 from os
import listdir
138 if not isdir(cptdir
):
139 fatal("checkpoint dir %s does not exist!", cptdir
)
142 if options
.at_instruction
or options
.simpoint
:
143 inst
= options
.checkpoint_restore
145 # assume workload 0 has the simpoint
146 if testsys
.cpu
[0].workload
[0].simpoint
== 0:
147 fatal('Unable to find simpoint')
148 inst
+= int(testsys
.cpu
[0].workload
[0].simpoint
)
150 checkpoint_dir
= joinpath(cptdir
, "cpt.%s.%s" % (options
.bench
, inst
))
151 if not exists(checkpoint_dir
):
152 fatal("Unable to find checkpoint directory %s", checkpoint_dir
)
154 elif options
.restore_simpoint_checkpoint
:
155 # Restore from SimPoint checkpoints
156 # Assumes that the checkpoint dir names are formatted as follows:
157 dirs
= listdir(cptdir
)
158 expr
= re
.compile('cpt\.simpoint_(\d+)_inst_(\d+)' +
159 '_weight_([\d\.e\-]+)_interval_(\d+)_warmup_(\d+)')
162 match
= expr
.match(dir)
167 cpt_num
= options
.checkpoint_restore
168 if cpt_num
> len(cpts
):
169 fatal('Checkpoint %d not found', cpt_num
)
170 checkpoint_dir
= joinpath(cptdir
, cpts
[cpt_num
- 1])
171 match
= expr
.match(cpts
[cpt_num
- 1])
173 index
= int(match
.group(1))
174 start_inst
= int(match
.group(2))
175 weight_inst
= float(match
.group(3))
176 interval_length
= int(match
.group(4))
177 warmup_length
= int(match
.group(5))
178 print("Resuming from", checkpoint_dir
)
179 simpoint_start_insts
= []
180 simpoint_start_insts
.append(warmup_length
)
181 simpoint_start_insts
.append(warmup_length
+ interval_length
)
182 testsys
.cpu
[0].simpoint_start_insts
= simpoint_start_insts
183 if testsys
.switch_cpus
!= None:
184 testsys
.switch_cpus
[0].simpoint_start_insts
= simpoint_start_insts
186 print("Resuming from SimPoint", end
=' ')
187 print("#%d, start_inst:%d, weight:%f, interval:%d, warmup:%d" %
188 (index
, start_inst
, weight_inst
, interval_length
, warmup_length
))
191 dirs
= listdir(cptdir
)
192 expr
= re
.compile('cpt\.([0-9]+)')
195 match
= expr
.match(dir)
197 cpts
.append(match
.group(1))
199 cpts
.sort(lambda a
,b
: cmp(long(a
), long(b
)))
201 cpt_num
= options
.checkpoint_restore
202 if cpt_num
> len(cpts
):
203 fatal('Checkpoint %d not found', cpt_num
)
205 cpt_starttick
= int(cpts
[cpt_num
- 1])
206 checkpoint_dir
= joinpath(cptdir
, "cpt.%s" % cpts
[cpt_num
- 1])
208 return cpt_starttick
, checkpoint_dir
210 def scriptCheckpoints(options
, maxtick
, cptdir
):
211 if options
.at_instruction
or options
.simpoint
:
212 checkpoint_inst
= int(options
.take_checkpoints
)
214 # maintain correct offset if we restored from some instruction
215 if options
.checkpoint_restore
!= None:
216 checkpoint_inst
+= options
.checkpoint_restore
218 print("Creating checkpoint at inst:%d" % (checkpoint_inst
))
219 exit_event
= m5
.simulate()
220 exit_cause
= exit_event
.getCause()
221 print("exit cause = %s" % exit_cause
)
223 # skip checkpoint instructions should they exist
224 while exit_cause
== "checkpoint":
225 exit_event
= m5
.simulate()
226 exit_cause
= exit_event
.getCause()
228 if exit_cause
== "a thread reached the max instruction count":
229 m5
.checkpoint(joinpath(cptdir
, "cpt.%s.%d" % \
230 (options
.bench
, checkpoint_inst
)))
231 print("Checkpoint written.")
234 when
, period
= options
.take_checkpoints
.split(",", 1)
239 exit_event
= m5
.simulate(when
- m5
.curTick())
240 exit_cause
= exit_event
.getCause()
241 while exit_cause
== "checkpoint":
242 exit_event
= m5
.simulate(when
- m5
.curTick())
243 exit_cause
= exit_event
.getCause()
245 if exit_cause
== "simulate() limit reached":
246 m5
.checkpoint(joinpath(cptdir
, "cpt.%d"))
250 max_checkpoints
= options
.max_checkpoints
252 while num_checkpoints
< max_checkpoints
and \
253 exit_cause
== "simulate() limit reached":
254 if (sim_ticks
+ period
) > maxtick
:
255 exit_event
= m5
.simulate(maxtick
- sim_ticks
)
256 exit_cause
= exit_event
.getCause()
259 exit_event
= m5
.simulate(period
)
260 exit_cause
= exit_event
.getCause()
262 while exit_event
.getCause() == "checkpoint":
263 exit_event
= m5
.simulate(sim_ticks
- m5
.curTick())
264 if exit_event
.getCause() == "simulate() limit reached":
265 m5
.checkpoint(joinpath(cptdir
, "cpt.%d"))
270 def benchCheckpoints(options
, maxtick
, cptdir
):
271 exit_event
= m5
.simulate(maxtick
- m5
.curTick())
272 exit_cause
= exit_event
.getCause()
275 max_checkpoints
= options
.max_checkpoints
277 while exit_cause
== "checkpoint":
278 m5
.checkpoint(joinpath(cptdir
, "cpt.%d"))
280 if num_checkpoints
== max_checkpoints
:
281 exit_cause
= "maximum %d checkpoints dropped" % max_checkpoints
284 exit_event
= m5
.simulate(maxtick
- m5
.curTick())
285 exit_cause
= exit_event
.getCause()
289 # Set up environment for taking SimPoint checkpoints
290 # Expecting SimPoint files generated by SimPoint 3.2
291 def parseSimpointAnalysisFile(options
, testsys
):
294 simpoint_filename
, weight_filename
, interval_length
, warmup_length
= \
295 options
.take_simpoint_checkpoints
.split(",", 3)
296 print("simpoint analysis file:", simpoint_filename
)
297 print("simpoint weight file:", weight_filename
)
298 print("interval length:", interval_length
)
299 print("warmup length:", warmup_length
)
301 interval_length
= int(interval_length
)
302 warmup_length
= int(warmup_length
)
304 # Simpoint analysis output starts interval counts with 0.
306 simpoint_start_insts
= []
308 # Read in SimPoint analysis files
309 simpoint_file
= open(simpoint_filename
)
310 weight_file
= open(weight_filename
)
312 line
= simpoint_file
.readline()
315 m
= re
.match("(\d+)\s+(\d+)", line
)
317 interval
= int(m
.group(1))
319 fatal('unrecognized line in simpoint file!')
321 line
= weight_file
.readline()
323 fatal('not enough lines in simpoint weight file!')
324 m
= re
.match("([0-9\.e\-]+)\s+(\d+)", line
)
326 weight
= float(m
.group(1))
328 fatal('unrecognized line in simpoint weight file!')
330 if (interval
* interval_length
- warmup_length
> 0):
331 starting_inst_count
= \
332 interval
* interval_length
- warmup_length
333 actual_warmup_length
= warmup_length
335 # Not enough room for proper warmup
336 # Just starting from the beginning
337 starting_inst_count
= 0
338 actual_warmup_length
= interval
* interval_length
340 simpoints
.append((interval
, weight
, starting_inst_count
,
341 actual_warmup_length
))
343 # Sort SimPoints by starting inst count
344 simpoints
.sort(key
=lambda obj
: obj
[2])
346 interval
, weight
, starting_inst_count
, actual_warmup_length
= s
347 print(str(interval
), str(weight
), starting_inst_count
,
348 actual_warmup_length
)
349 simpoint_start_insts
.append(starting_inst_count
)
351 print("Total # of simpoints:", len(simpoints
))
352 testsys
.cpu
[0].simpoint_start_insts
= simpoint_start_insts
354 return (simpoints
, interval_length
)
356 def takeSimpointCheckpoints(simpoints
, interval_length
, cptdir
):
359 last_chkpnt_inst_count
= -1
360 for simpoint
in simpoints
:
361 interval
, weight
, starting_inst_count
, actual_warmup_length
= simpoint
362 if starting_inst_count
== last_chkpnt_inst_count
:
363 # checkpoint starting point same as last time
364 # (when warmup period longer than starting point)
365 exit_cause
= "simpoint starting point found"
368 exit_event
= m5
.simulate()
370 # skip checkpoint instructions should they exist
371 while exit_event
.getCause() == "checkpoint":
372 print("Found 'checkpoint' exit event...ignoring...")
373 exit_event
= m5
.simulate()
375 exit_cause
= exit_event
.getCause()
376 code
= exit_event
.getCode()
378 if exit_cause
== "simpoint starting point found":
379 m5
.checkpoint(joinpath(cptdir
,
380 "cpt.simpoint_%02d_inst_%d_weight_%f_interval_%d_warmup_%d"
381 % (index
, starting_inst_count
, weight
, interval_length
,
382 actual_warmup_length
)))
383 print("Checkpoint #%d written. start inst:%d weight:%f" %
384 (num_checkpoints
, starting_inst_count
, weight
))
386 last_chkpnt_inst_count
= starting_inst_count
391 print('Exiting @ tick %i because %s' % (m5
.curTick(), exit_cause
))
392 print("%d checkpoints taken" % num_checkpoints
)
395 def restoreSimpointCheckpoint():
396 exit_event
= m5
.simulate()
397 exit_cause
= exit_event
.getCause()
399 if exit_cause
== "simpoint starting point found":
400 print("Warmed up! Dumping and resetting stats!")
404 exit_event
= m5
.simulate()
405 exit_cause
= exit_event
.getCause()
407 if exit_cause
== "simpoint starting point found":
408 print("Done running SimPoint!")
409 sys
.exit(exit_event
.getCode())
411 print('Exiting @ tick %i because %s' % (m5
.curTick(), exit_cause
))
412 sys
.exit(exit_event
.getCode())
414 def repeatSwitch(testsys
, repeat_switch_cpu_list
, maxtick
, switch_freq
):
415 print("starting switch loop")
417 exit_event
= m5
.simulate(switch_freq
)
418 exit_cause
= exit_event
.getCause()
420 if exit_cause
!= "simulate() limit reached":
423 m5
.switchCpus(testsys
, repeat_switch_cpu_list
)
426 for old_cpu
, new_cpu
in repeat_switch_cpu_list
:
427 tmp_cpu_list
.append((new_cpu
, old_cpu
))
428 repeat_switch_cpu_list
= tmp_cpu_list
430 if (maxtick
- m5
.curTick()) <= switch_freq
:
431 exit_event
= m5
.simulate(maxtick
- m5
.curTick())
434 def run(options
, root
, testsys
, cpu_class
):
435 if options
.checkpoint_dir
:
436 cptdir
= options
.checkpoint_dir
437 elif m5
.options
.outdir
:
438 cptdir
= m5
.options
.outdir
442 if options
.fast_forward
and options
.checkpoint_restore
!= None:
443 fatal("Can't specify both --fast-forward and --checkpoint-restore")
445 if options
.standard_switch
and not options
.caches
:
446 fatal("Must specify --caches when using --standard-switch")
448 if options
.standard_switch
and options
.repeat_switch
:
449 fatal("Can't specify both --standard-switch and --repeat-switch")
451 if options
.repeat_switch
and options
.take_checkpoints
:
452 fatal("Can't specify both --repeat-switch and --take-checkpoints")
454 np
= options
.num_cpus
457 if options
.prog_interval
:
459 testsys
.cpu
[i
].progress_interval
= options
.prog_interval
463 testsys
.cpu
[i
].max_insts_any_thread
= options
.maxinsts
466 switch_cpus
= [cpu_class(switched_out
=True, cpu_id
=(i
))
470 if options
.fast_forward
:
471 testsys
.cpu
[i
].max_insts_any_thread
= int(options
.fast_forward
)
472 switch_cpus
[i
].system
= testsys
473 switch_cpus
[i
].workload
= testsys
.cpu
[i
].workload
474 switch_cpus
[i
].clk_domain
= testsys
.cpu
[i
].clk_domain
475 switch_cpus
[i
].progress_interval
= \
476 testsys
.cpu
[i
].progress_interval
477 switch_cpus
[i
].isa
= testsys
.cpu
[i
].isa
480 switch_cpus
[i
].max_insts_any_thread
= options
.maxinsts
481 # Add checker cpu if selected
483 switch_cpus
[i
].addCheckerCpu()
485 bpClass
= ObjectList
.bp_list
.get(options
.bp_type
)
486 switch_cpus
[i
].branchPred
= bpClass()
487 if options
.indirect_bp_type
:
488 IndirectBPClass
= ObjectList
.indirect_bp_list
.get(
489 options
.indirect_bp_type
)
490 switch_cpus
[i
].branchPred
.indirectBranchPred
= \
493 # If elastic tracing is enabled attach the elastic trace probe
495 if options
.elastic_trace_en
:
496 CpuConfig
.config_etrace(cpu_class
, switch_cpus
, options
)
498 testsys
.switch_cpus
= switch_cpus
499 switch_cpu_list
= [(testsys
.cpu
[i
], switch_cpus
[i
]) for i
in range(np
)]
501 if options
.repeat_switch
:
502 switch_class
= getCPUClass(options
.cpu_type
)[0]
503 if switch_class
.require_caches() and \
505 print("%s: Must be used with caches" % str(switch_class
))
507 if not switch_class
.support_take_over():
508 print("%s: CPU switching not supported" % str(switch_class
))
511 repeat_switch_cpus
= [switch_class(switched_out
=True, \
512 cpu_id
=(i
)) for i
in range(np
)]
515 repeat_switch_cpus
[i
].system
= testsys
516 repeat_switch_cpus
[i
].workload
= testsys
.cpu
[i
].workload
517 repeat_switch_cpus
[i
].clk_domain
= testsys
.cpu
[i
].clk_domain
518 repeat_switch_cpus
[i
].isa
= testsys
.cpu
[i
].isa
521 repeat_switch_cpus
[i
].max_insts_any_thread
= options
.maxinsts
524 repeat_switch_cpus
[i
].addCheckerCpu()
526 testsys
.repeat_switch_cpus
= repeat_switch_cpus
529 repeat_switch_cpu_list
= [(switch_cpus
[i
], repeat_switch_cpus
[i
])
532 repeat_switch_cpu_list
= [(testsys
.cpu
[i
], repeat_switch_cpus
[i
])
535 if options
.standard_switch
:
536 switch_cpus
= [TimingSimpleCPU(switched_out
=True, cpu_id
=(i
))
538 switch_cpus_1
= [DerivO3CPU(switched_out
=True, cpu_id
=(i
))
542 switch_cpus
[i
].system
= testsys
543 switch_cpus_1
[i
].system
= testsys
544 switch_cpus
[i
].workload
= testsys
.cpu
[i
].workload
545 switch_cpus_1
[i
].workload
= testsys
.cpu
[i
].workload
546 switch_cpus
[i
].clk_domain
= testsys
.cpu
[i
].clk_domain
547 switch_cpus_1
[i
].clk_domain
= testsys
.cpu
[i
].clk_domain
548 switch_cpus
[i
].isa
= testsys
.cpu
[i
].isa
549 switch_cpus_1
[i
].isa
= testsys
.cpu
[i
].isa
551 # if restoring, make atomic cpu simulate only a few instructions
552 if options
.checkpoint_restore
!= None:
553 testsys
.cpu
[i
].max_insts_any_thread
= 1
554 # Fast forward to specified location if we are not restoring
555 elif options
.fast_forward
:
556 testsys
.cpu
[i
].max_insts_any_thread
= int(options
.fast_forward
)
557 # Fast forward to a simpoint (warning: time consuming)
558 elif options
.simpoint
:
559 if testsys
.cpu
[i
].workload
[0].simpoint
== 0:
560 fatal('simpoint not found')
561 testsys
.cpu
[i
].max_insts_any_thread
= \
562 testsys
.cpu
[i
].workload
[0].simpoint
563 # No distance specified, just switch
565 testsys
.cpu
[i
].max_insts_any_thread
= 1
568 if options
.warmup_insts
:
569 switch_cpus
[i
].max_insts_any_thread
= options
.warmup_insts
573 switch_cpus_1
[i
].max_insts_any_thread
= options
.maxinsts
575 # attach the checker cpu if selected
577 switch_cpus
[i
].addCheckerCpu()
578 switch_cpus_1
[i
].addCheckerCpu()
580 testsys
.switch_cpus
= switch_cpus
581 testsys
.switch_cpus_1
= switch_cpus_1
583 (testsys
.cpu
[i
], switch_cpus
[i
]) for i
in range(np
)
586 (switch_cpus
[i
], switch_cpus_1
[i
]) for i
in range(np
)
589 # set the checkpoint in the cpu before m5.instantiate is called
590 if options
.take_checkpoints
!= None and \
591 (options
.simpoint
or options
.at_instruction
):
592 offset
= int(options
.take_checkpoints
)
593 # Set an instruction break point
596 if testsys
.cpu
[i
].workload
[0].simpoint
== 0:
597 fatal('no simpoint for testsys.cpu[%d].workload[0]', i
)
598 checkpoint_inst
= int(testsys
.cpu
[i
].workload
[0].simpoint
) + offset
599 testsys
.cpu
[i
].max_insts_any_thread
= checkpoint_inst
600 # used for output below
601 options
.take_checkpoints
= checkpoint_inst
603 options
.take_checkpoints
= offset
604 # Set all test cpus with the right number of instructions
605 # for the upcoming simulation
607 testsys
.cpu
[i
].max_insts_any_thread
= offset
609 if options
.take_simpoint_checkpoints
!= None:
610 simpoints
, interval_length
= parseSimpointAnalysisFile(options
, testsys
)
612 checkpoint_dir
= None
613 if options
.checkpoint_restore
:
614 cpt_starttick
, checkpoint_dir
= findCptDir(options
, cptdir
, testsys
)
615 root
.apply_config(options
.param
)
616 m5
.instantiate(checkpoint_dir
)
618 # Initialization is complete. If we're not in control of simulation
619 # (that is, if we're a slave simulator acting as a component in another
620 # 'master' simulator) then we're done here. The other simulator will
621 # call simulate() directly. --initialize-only is used to indicate this.
622 if options
.initialize_only
:
625 # Handle the max tick settings now that tick frequency was resolved
626 # during system instantiation
627 # NOTE: the maxtick variable here is in absolute ticks, so it must
628 # include any simulated ticks before a checkpoint
629 explicit_maxticks
= 0
630 maxtick_from_abs
= m5
.MaxTick
631 maxtick_from_rel
= m5
.MaxTick
632 maxtick_from_maxtime
= m5
.MaxTick
633 if options
.abs_max_tick
:
634 maxtick_from_abs
= options
.abs_max_tick
635 explicit_maxticks
+= 1
636 if options
.rel_max_tick
:
637 maxtick_from_rel
= options
.rel_max_tick
638 if options
.checkpoint_restore
:
639 # NOTE: this may need to be updated if checkpoints ever store
640 # the ticks per simulated second
641 maxtick_from_rel
+= cpt_starttick
642 if options
.at_instruction
or options
.simpoint
:
643 warn("Relative max tick specified with --at-instruction or" \
644 " --simpoint\n These options don't specify the " \
645 "checkpoint start tick, so assuming\n you mean " \
647 explicit_maxticks
+= 1
649 maxtick_from_maxtime
= m5
.ticks
.fromSeconds(options
.maxtime
)
650 explicit_maxticks
+= 1
651 if explicit_maxticks
> 1:
652 warn("Specified multiple of --abs-max-tick, --rel-max-tick, --maxtime."\
654 maxtick
= min([maxtick_from_abs
, maxtick_from_rel
, maxtick_from_maxtime
])
656 if options
.checkpoint_restore
!= None and maxtick
< cpt_starttick
:
657 fatal("Bad maxtick (%d) specified: " \
658 "Checkpoint starts starts from tick: %d", maxtick
, cpt_starttick
)
660 if options
.standard_switch
or cpu_class
:
661 if options
.standard_switch
:
662 print("Switch at instruction count:%s" %
663 str(testsys
.cpu
[0].max_insts_any_thread
))
664 exit_event
= m5
.simulate()
665 elif cpu_class
and options
.fast_forward
:
666 print("Switch at instruction count:%s" %
667 str(testsys
.cpu
[0].max_insts_any_thread
))
668 exit_event
= m5
.simulate()
670 print("Switch at curTick count:%s" % str(10000))
671 exit_event
= m5
.simulate(10000)
672 print("Switched CPUS @ tick %s" % (m5
.curTick()))
674 m5
.switchCpus(testsys
, switch_cpu_list
)
676 if options
.standard_switch
:
677 print("Switch at instruction count:%d" %
678 (testsys
.switch_cpus
[0].max_insts_any_thread
))
680 #warmup instruction count may have already been set
681 if options
.warmup_insts
:
682 exit_event
= m5
.simulate()
684 exit_event
= m5
.simulate(options
.standard_switch
)
685 print("Switching CPUS @ tick %s" % (m5
.curTick()))
686 print("Simulation ends instruction count:%d" %
687 (testsys
.switch_cpus_1
[0].max_insts_any_thread
))
688 m5
.switchCpus(testsys
, switch_cpu_list1
)
690 # If we're taking and restoring checkpoints, use checkpoint_dir
691 # option only for finding the checkpoints to restore from. This
692 # lets us test checkpointing by restoring from one set of
693 # checkpoints, generating a second set, and then comparing them.
694 if (options
.take_checkpoints
or options
.take_simpoint_checkpoints
) \
695 and options
.checkpoint_restore
:
697 if m5
.options
.outdir
:
698 cptdir
= m5
.options
.outdir
702 if options
.take_checkpoints
!= None :
703 # Checkpoints being taken via the command line at <when> and at
704 # subsequent periods of <period>. Checkpoint instructions
705 # received from the benchmark running are ignored and skipped in
706 # favor of command line checkpoint instructions.
707 exit_event
= scriptCheckpoints(options
, maxtick
, cptdir
)
709 # Take SimPoint checkpoints
710 elif options
.take_simpoint_checkpoints
!= None:
711 takeSimpointCheckpoints(simpoints
, interval_length
, cptdir
)
713 # Restore from SimPoint checkpoints
714 elif options
.restore_simpoint_checkpoint
!= None:
715 restoreSimpointCheckpoint()
718 if options
.fast_forward
:
720 print("**** REAL SIMULATION ****")
722 # If checkpoints are being taken, then the checkpoint instruction
723 # will occur in the benchmark code it self.
724 if options
.repeat_switch
and maxtick
> options
.repeat_switch
:
725 exit_event
= repeatSwitch(testsys
, repeat_switch_cpu_list
,
726 maxtick
, options
.repeat_switch
)
728 exit_event
= benchCheckpoints(options
, maxtick
, cptdir
)
730 print('Exiting @ tick %i because %s' %
731 (m5
.curTick(), exit_event
.getCause()))
732 if options
.checkpoint_at_end
:
733 m5
.checkpoint(joinpath(cptdir
, "cpt.%d"))
735 if exit_event
.getCode() != 0:
736 print("Simulated exit code not 0! Exit code is", exit_event
.getCode())