configs/ruby/Ruby.py

   1 # Copyright (c) 2012, 2017-2018 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
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  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
  14 # Copyright (c) 2009 Advanced Micro Devices, Inc.
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  39
  40 import math
  41 import m5
  42 from m5.objects import *
  43 from m5.defines import buildEnv
  44 from m5.util import addToPath, fatal
  45
  46 addToPath('../')
  47
  48 from common import ObjectList
  49 from common import MemConfig
  50 from common import FileSystemConfig
  51
  52 from topologies import *
  53 from network import Network
  54
  55 def define_options(parser):
  56     # By default, ruby uses the simple timing cpu
  57     parser.set_defaults(cpu_type="TimingSimpleCPU")
  58
  59     parser.add_option("--ruby-clock", action="store", type="string",
  60                       default='2GHz',
  61                       help="Clock for blocks running at Ruby system's speed")
  62
  63     parser.add_option("--access-backing-store", action="store_true", default=False,
  64                       help="Should ruby maintain a second copy of memory")
  65
  66     # Options related to cache structure
  67     parser.add_option("--ports", action="store", type="int", default=4,
  68                       help="used of transitions per cycle which is a proxy \
  69                             for the number of ports.")
  70
  71     # network options are in network/Network.py
  72
  73     # ruby mapping options
  74     parser.add_option("--numa-high-bit", type="int", default=0,
  75                       help="high order address bit to use for numa mapping. " \
  76                            "0 = highest bit, not specified = lowest bit")
  77     parser.add_option("--interleaving-bits", type="int", default=0,
  78                       help="number of bits to specify interleaving " \
  79                            "in directory, memory controllers and caches. "
  80                            "0 = not specified")
  81     parser.add_option("--xor-low-bit", type="int", default=20,
  82                       help="hashing bit for channel selection" \
  83                            "see MemConfig for explanation of the default"\
  84                            "parameter. If set to 0, xor_high_bit is also"\
  85                            "set to 0.")
  86
  87     parser.add_option("--recycle-latency", type="int", default=10,
  88                       help="Recycle latency for ruby controller input buffers")
  89
  90     protocol = buildEnv['PROTOCOL']
  91     exec("from . import %s" % protocol)
  92     eval("%s.define_options(parser)" % protocol)
  93     Network.define_options(parser)
  94
  95 def setup_memory_controllers(system, ruby, dir_cntrls, options):
  96     if (options.numa_high_bit):
  97         block_size_bits = options.numa_high_bit + 1 - \
  98                           int(math.log(options.num_dirs, 2))
  99         ruby.block_size_bytes = 2 ** (block_size_bits)
 100     else:
 101         ruby.block_size_bytes = options.cacheline_size
 102
 103     ruby.memory_size_bits = 48
 104
 105     index = 0
 106     mem_ctrls = []
 107     crossbars = []
 108
 109     if options.numa_high_bit:
 110         dir_bits = int(math.log(options.num_dirs, 2))
 111         intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1)
 112     else:
 113         # if the numa_bit is not specified, set the directory bits as the
 114         # lowest bits above the block offset bits
 115         intlv_size = options.cacheline_size
 116
 117     # Sets bits to be used for interleaving.  Creates memory controllers
 118     # attached to a directory controller.  A separate controller is created
 119     # for each address range as the abstract memory can handle only one
 120     # contiguous address range as of now.
 121     for dir_cntrl in dir_cntrls:
 122         crossbar = None
 123         if len(system.mem_ranges) > 1:
 124             crossbar = IOXBar()
 125             crossbars.append(crossbar)
 126             dir_cntrl.memory = crossbar.slave
 127
 128         dir_ranges = []
 129         for r in system.mem_ranges:
 130             mem_type = ObjectList.mem_list.get(options.mem_type)
 131             dram_intf = MemConfig.create_mem_intf(mem_type, r, index,
 132                 options.num_dirs, int(math.log(options.num_dirs, 2)),
 133                 intlv_size, options.xor_low_bit)
 134             mem_ctrl = m5.objects.MemCtrl(dram = dram_intf)
 135
 136             if options.access_backing_store:
 137                 dram_intf.kvm_map=False
 138
 139             mem_ctrls.append(mem_ctrl)
 140             dir_ranges.append(mem_ctrl.dram.range)
 141
 142             if crossbar != None:
 143                 mem_ctrl.port = crossbar.master
 144             else:
 145                 mem_ctrl.port = dir_cntrl.memory
 146
 147             # Enable low-power DRAM states if option is set
 148             if issubclass(mem_type, DRAMInterface):
 149                 mem_ctrl.dram.enable_dram_powerdown = \
 150                         options.enable_dram_powerdown
 151
 152         index += 1
 153         dir_cntrl.addr_ranges = dir_ranges
 154
 155     system.mem_ctrls = mem_ctrls
 156
 157     if len(crossbars) > 0:
 158         ruby.crossbars = crossbars
 159
 160
 161 def create_topology(controllers, options):
 162     """ Called from create_system in configs/ruby/<protocol>.py
 163         Must return an object which is a subclass of BaseTopology
 164         found in configs/topologies/BaseTopology.py
 165         This is a wrapper for the legacy topologies.
 166     """
 167     exec("import topologies.%s as Topo" % options.topology)
 168     topology = eval("Topo.%s(controllers)" % options.topology)
 169     return topology
 170
 171 def create_system(options, full_system, system, piobus = None, dma_ports = [],
 172                   bootmem=None):
 173
 174     system.ruby = RubySystem()
 175     ruby = system.ruby
 176
 177     # Generate pseudo filesystem
 178     FileSystemConfig.config_filesystem(system, options)
 179
 180     # Create the network object
 181     (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \
 182         Network.create_network(options, ruby)
 183     ruby.network = network
 184
 185     protocol = buildEnv['PROTOCOL']
 186     exec("from . import %s" % protocol)
 187     try:
 188         (cpu_sequencers, dir_cntrls, topology) = \
 189              eval("%s.create_system(options, full_system, system, dma_ports,\
 190                                     bootmem, ruby)"
 191                   % protocol)
 192     except:
 193         print("Error: could not create sytem for ruby protocol %s" % protocol)
 194         raise
 195
 196     # Create the network topology
 197     topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
 198             RouterClass)
 199
 200     # Register the topology elements with faux filesystem (SE mode only)
 201     if not full_system:
 202         topology.registerTopology(options)
 203
 204
 205     # Initialize network based on topology
 206     Network.init_network(options, network, InterfaceClass)
 207
 208     # Create a port proxy for connecting the system port. This is
 209     # independent of the protocol and kept in the protocol-agnostic
 210     # part (i.e. here).
 211     sys_port_proxy = RubyPortProxy(ruby_system = ruby)
 212     if piobus is not None:
 213         sys_port_proxy.pio_master_port = piobus.slave
 214
 215     # Give the system port proxy a SimObject parent without creating a
 216     # full-fledged controller
 217     system.sys_port_proxy = sys_port_proxy
 218
 219     # Connect the system port for loading of binaries etc
 220     system.system_port = system.sys_port_proxy.slave
 221
 222     setup_memory_controllers(system, ruby, dir_cntrls, options)
 223
 224     # Connect the cpu sequencers and the piobus
 225     if piobus != None:
 226         for cpu_seq in cpu_sequencers:
 227             cpu_seq.connectIOPorts(piobus)
 228
 229     ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
 230     ruby._cpu_ports = cpu_sequencers
 231     ruby.num_of_sequencers = len(cpu_sequencers)
 232
 233     # Create a backing copy of physical memory in case required
 234     if options.access_backing_store:
 235         ruby.access_backing_store = True
 236         ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
 237                                      in_addr_map=False)
 238
 239 def create_directories(options, bootmem, ruby_system, system):
 240     dir_cntrl_nodes = []
 241     for i in range(options.num_dirs):
 242         dir_cntrl = Directory_Controller()
 243         dir_cntrl.version = i
 244         dir_cntrl.directory = RubyDirectoryMemory()
 245         dir_cntrl.ruby_system = ruby_system
 246
 247         exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
 248         dir_cntrl_nodes.append(dir_cntrl)
 249
 250     if bootmem is not None:
 251         rom_dir_cntrl = Directory_Controller()
 252         rom_dir_cntrl.directory = RubyDirectoryMemory()
 253         rom_dir_cntrl.ruby_system = ruby_system
 254         rom_dir_cntrl.version = i + 1
 255         rom_dir_cntrl.memory = bootmem.port
 256         rom_dir_cntrl.addr_ranges = bootmem.range
 257         return (dir_cntrl_nodes, rom_dir_cntrl)
 258
 259     return (dir_cntrl_nodes, None)
 260
 261 def send_evicts(options):
 262     # currently, 2 scenarios warrant forwarding evictions to the CPU:
 263     # 1. The O3 model must keep the LSQ coherent with the caches
 264     # 2. The x86 mwait instruction is built on top of coherence invalidations
 265     # 3. The local exclusive monitor in ARM systems
 266     if options.cpu_type == "DerivO3CPU" or \
 267        buildEnv['TARGET_ISA'] in ('x86', 'arm'):
 268         return True
 269     return False